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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [sim/] [testbenches/] [xml/] [T6502_def_tb.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Mos6502
T6502
def_tb
 
 
 

 

  elab_verilog
  103.0
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog

 
 
 

  trace_bus
  103.0
  none
  :*Simulation:*
  ./tools/verilog/trace_bus
    
    
      path
      root.dut.cpu
    
    
      bus_name
      cpu
    
  

 
 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      tb.tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 

 
 
 
 

 
 
 
 
 

 
              
              Params
              
              
                                   spirit:library="Mos6502"
                                   spirit:name="T6502"
                                   spirit:version="def_dut.params"/>
              
              
 
 
 
              
              Bfm
              
              
                                   spirit:library="Mos6502"
                                   spirit:name="T6502"
                                   spirit:version="bfm"/>
              
              
 
 
 
 
 
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              common
              common
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim
              :*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              lint
              :*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 

 
 
 
 
 

 
 
 
   
      fs-common
 
      
        
        ../verilog/sram.load
        verilogSourcefragment
      
 
 
      
        
        ../verilog/tb.ext_m
        verilogSourcefragment
      
 
 
   
 
 
 
 
   
      fs-sim
 
 
 
      
        
        ../verilog/common/tb.tb
        verilogSourcemodule
      
 
   
 
 
 
   
      fs-lint
 
      
        
        ../verilog/common/tb.tb
        verilogSourcemodule
      
 
 
 
   
 
 
 
 

 
 
 

 
 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [sim/] [testbenches/] [xml/] [T6502_def_tb.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Mos6502`
39			`T6502`
40			`def_tb`
41
42
43
44
45
46
47			`elab_verilog`
48			`103.0`
49			`none`
50			`:Simulation:`
51			`./tools/verilog/elab_verilog`
52
53
54
55
56
57			`trace_bus`
58			`103.0`
59			`none`
60			`:Simulation:`
61			`./tools/verilog/trace_bus`
62
63
64			`path`
65			`root.dut.cpu`
66
67
68			`bus_name`
69			`cpu`
70
71
72
73
74
75
76
77
78
79			`gen_verilog`
80			`104.0`
81			`none`
82			`common`
83			`./tools/verilog/gen_verilog`
84
85
86			`destination`
87			`tb.tb`
88
89
90			`dest_dir`
91			`../verilog`
92
93
94			`top`
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115			`Params`
116
117
118			`spirit:library="Mos6502"`
119			`spirit:name="T6502"`
120			`spirit:version="def_dut.params"/>`
121
122
123
124
125
126
127			`Bfm`
128
129
130			`spirit:library="Mos6502"`
131			`spirit:name="T6502"`
132			`spirit:version="bfm"/>`
133
134
135
136
137
138
139
140
141
142
143			`icarus`
144
145
146			`spirit:library="Testbench"`
147			`spirit:name="toolflow"`
148			`spirit:version="icarus"/>`
149
150
151
152
153
154
155
156			`common`
157			`common`
158			`Verilog`
159
160
161			`fs-common`
162
163
164
165
166
167			`sim`
168			`:Simulation:`
169			`Verilog`
170
171
172			`fs-sim`
173
174
175
176
177
178			`lint`
179			`:Lint:`
180			`Verilog`
181
182
183			`fs-lint`
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202			`fs-common`
203
204
205
206			`../verilog/sram.load`
207			`verilogSourcefragment`
208
209
210
211
212
213			`../verilog/tb.ext_m`
214			`verilogSourcefragment`
215
216
217
218
219
220
221
222
223
224			`fs-sim`
225
226
227
228
229
230			`../verilog/common/tb.tb`
231			`verilogSourcemodule`
232
233
234
235
236
237
238
239			`fs-lint`
240
241
242
243			`../verilog/common/tb.tb`
244			`verilogSourcemodule`
245
246
247
248
249
250
251
252
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