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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [sim/] [testbenches/] [xml/] [T6502_def_tb.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Mos6502
T6502
def_tb
 
 
 

 
 
 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      configuration
      default
    
    
      destination
      tb.tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 

 
 
 
 

 
 
 
 
 

 
              
              Params
              
              
                                   spirit:library="Mos6502"
                                   spirit:name="T6502"
                                   spirit:version="def_dut.params"/>
              
              
 
 
 
              
              Bfm
              
              
                                   spirit:library="Mos6502"
                                   spirit:name="T6502"
                                   spirit:version="bfm"/>
              
              
 
 
 
 
 
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              common
              common
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim
              :*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              lint
              :*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 

 
 
 
 
 

 
 
 
   
      fs-common
 
      
        
        ../verilog/sram.load
        verilogSourcefragment
      
 
 
      
        
        ../verilog/tb.ext_m
        verilogSourcefragment
      
 
 
   
 
 
 
 
   
      fs-sim
 
 
 
      
        
        ../verilog/common/tb.tb
        verilogSourcemodule
      
 
   
 
 
 
   
      fs-lint
 
      
        
        ../verilog/common/tb.tb
        verilogSourcemodule
      
 
 
 
   
 
 
 
 

 
 
 

 
 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [sim/] [testbenches/] [xml/] [T6502_def_tb.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Mos6502`
39			`T6502`
40			`def_tb`
41
42
43
44
45
46
47
48
49
50
51
52			`gen_verilog`
53			`104.0`
54			`none`
55			`common`
56			`./tools/verilog/gen_verilog`
57
58
59	133	jt_eaton	`configuration`
60			`default`
61
62
63	131	jt_eaton	`destination`
64			`tb.tb`
65
66
67			`dest_dir`
68			`../verilog`
69
70
71			`top`
72
73
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92			`Params`
93
94
95			`spirit:library="Mos6502"`
96			`spirit:name="T6502"`
97			`spirit:version="def_dut.params"/>`
98
99
100
101
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103
104			`Bfm`
105
106
107			`spirit:library="Mos6502"`
108			`spirit:name="T6502"`
109			`spirit:version="bfm"/>`
110
111
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116
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118
119
120			`icarus`
121
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123			`spirit:library="Testbench"`
124			`spirit:name="toolflow"`
125			`spirit:version="icarus"/>`
126
127
128
129
130
131
132
133			`common`
134			`common`
135			`Verilog`
136
137
138			`fs-common`
139
140
141
142
143
144			`sim`
145			`:Simulation:`
146			`Verilog`
147
148
149			`fs-sim`
150
151
152
153
154
155			`lint`
156			`:Lint:`
157			`Verilog`
158
159
160			`fs-lint`
161
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179			`fs-common`
180
181
182
183			`../verilog/sram.load`
184			`verilogSourcefragment`
185
186
187
188
189
190			`../verilog/tb.ext_m`
191			`verilogSourcefragment`
192
193
194
195
196
197
198
199
200
201			`fs-sim`
202
203
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207			`../verilog/common/tb.tb`
208			`verilogSourcemodule`
209
210
211
212
213
214
215
216			`fs-lint`
217
218
219
220			`../verilog/common/tb.tb`
221			`verilogSourcemodule`
222
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