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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [sim/] [testbenches/] [xml/] [T6502_def_tb.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Mos6502
T6502
def_tb
 
 
 

 
 
 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      T6502_def_tb
    
  

 
 
 

 
 
 
 

 
 
 
 
 

 
              
              Params
              
              
                                   spirit:library="Mos6502"
                                   spirit:name="T6502"
                                   spirit:version="def_dut.params"/>
              
              
 
 
 
              
              Bfm
              
              
                                   spirit:library="Mos6502"
                                   spirit:name="T6502"
                                   spirit:version="bfm"/>
              
              
 
 
 
 
 
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              common
              common
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim
              :*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              lint
              :*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 

 
 
 
 
 

 
 
 
   
      fs-common
 
      
        
        ../verilog/sram.load
        verilogSourcefragment
      
 
 
      
        
        ../verilog/tb.ext_m
        verilogSourcefragment
      
 
 
   
 
 
 
 
   
      fs-sim
 
 
 
      
        
        ../verilog/common/T6502_def_tb
        verilogSourcemodule
      
 
   
 
 
 
   
      fs-lint
 
      
        
        ../verilog/common/T6502_def_tb
        verilogSourcemodule
      
 
 
 
   
 
 
 
 

 
 
 

 
 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [sim/] [testbenches/] [xml/] [T6502_def_tb.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
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31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Mos6502`
39			`T6502`
40			`def_tb`
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52			`gen_verilog`
53			`104.0`
54			`none`
55			`common`
56			`./tools/verilog/gen_verilog`
57
58
59			`destination`
60	134	jt_eaton	`T6502_def_tb`
61	131	jt_eaton
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81			`Params`
82
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84			`spirit:library="Mos6502"`
85			`spirit:name="T6502"`
86			`spirit:version="def_dut.params"/>`
87
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93			`Bfm`
94
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96			`spirit:library="Mos6502"`
97			`spirit:name="T6502"`
98			`spirit:version="bfm"/>`
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109			`icarus`
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112			`spirit:library="Testbench"`
113			`spirit:name="toolflow"`
114			`spirit:version="icarus"/>`
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122			`common`
123			`common`
124			`Verilog`
125
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127			`fs-common`
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133			`sim`
134			`:Simulation:`
135			`Verilog`
136
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138			`fs-sim`
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144			`lint`
145			`:Lint:`
146			`Verilog`
147
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149			`fs-lint`
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168			`fs-common`
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172			`../verilog/sram.load`
173			`verilogSourcefragment`
174
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179			`../verilog/tb.ext_m`
180			`verilogSourcefragment`
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190			`fs-sim`
191
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196	134	jt_eaton	`../verilog/common/T6502_def_tb`
197	131	jt_eaton	`verilogSourcemodule`
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205			`fs-lint`
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209	134	jt_eaton	`../verilog/common/T6502_def_tb`
210	131	jt_eaton	`verilogSourcemodule`
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