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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [sim/] [testbenches/] [xml/] [T6502_def_vtb.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Mos6502
T6502
def_vtb
 
 
 

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      tb.vtb
    
  

 
 
 
 

 
 
 
 
 


    TIMEOUT10000

 
 
       
 
              
              Params
              
              
                                   spirit:library="Mos6502"
                                   spirit:name="T6502"
                                   spirit:version="def_dut.params"/>
              
 
              
 
 
 
 
 
              
              verilator
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilator"/>
              
              
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 
 
 

 
 
 

 
 
 
   
      fs-common
 
      
        
        ../verilog/sram.load
        verilogSourcefragment
      
 
 
      
        
        ../verilog/tb.int_m
        verilogSourcefragment
      
 
 
      
        
        ../verilog/top.vtb
        verilogSourcefragment
      
 
   
 
 
 
 
 
   
      fs-syn
 
      
        
        ../verilog/common/tb.vtb
        verilogSourcemodule
      
 
 
   
 
 
   
      fs-lint
 
      
        
        ../verilog/common/tb.vtb
        verilogSourcemodule
      
 
 
   
 
 
 

 
 
 
 
 
 
 
 

 
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Mos6502`
39			`T6502`
40			`def_vtb`
41
42
43
44
45
46
47
48
49			`gen_verilog`
50			`104.0`
51			`none`
52			`common`
53			`./tools/verilog/gen_verilog`
54
55
56			`destination`
57			`tb.vtb`
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73			`TIMEOUT10000`
74
75
76
77
78
79
80			`Params`
81
82
83			`spirit:library="Mos6502"`
84			`spirit:name="T6502"`
85			`spirit:version="def_dut.params"/>`
86
87
88
89
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91
92
93
94
95			`verilator`
96
97
98			`spirit:library="Testbench"`
99			`spirit:name="toolflow"`
100			`spirit:version="verilator"/>`
101
102
103
104
105
106
107			`commoncommon`
108			`Verilog`
109
110
111			`fs-common`
112
113
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116
117
118
119			`syn:Synthesis:`
120			`Verilog`
121
122
123			`fs-syn`
124
125
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127
128
129			`lint:Lint:`
130			`Verilog`
131
132
133			`fs-lint`
134
135
136
137
138
139
140
141
142
143
144
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153			`fs-common`
154
155
156
157			`../verilog/sram.load`
158			`verilogSourcefragment`
159
160
161
162
163
164			`../verilog/tb.int_m`
165			`verilogSourcefragment`
166
167
168
169
170
171			`../verilog/top.vtb`
172			`verilogSourcefragment`
173
174
175
176
177
178
179
180
181
182			`fs-syn`
183
184
185
186			`../verilog/common/tb.vtb`
187			`verilogSourcemodule`
188
189
190
191
192
193
194
195			`fs-lint`
196
197
198
199			`../verilog/common/tb.vtb`
200			`verilogSourcemodule`
201
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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [sim/] [testbenches/] [xml/] [T6502_def_vtb.xml] - Blame information for rev 134