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module `VARIANT`ALU
 
(
 
 
input   wire           clk,
input   wire           reset,
input   wire           enable,
 
input   wire           alu_enable,
 
input   wire  [7:0]    alu_op_b,
input   wire  [7:0]    psp_res,
 
input   wire  [7:0]    brn_value,
input   wire  [7:0]    brn_enable,
input   wire  [2:0]    dest,
input   wire           relative,
input   wire  [2:0]    alu_mode,
input   wire  [4:0]    alu_status_update,
input   wire  [2:0]    alu_op_a_sel,
input   wire           alu_op_b_inv,
input   wire  [1:0]    alu_op_c_sel,
 
 
output   reg           branch_inst,
output   reg  [7:0]    alu_result,
output   reg  [7:0]    alu_status,
output   reg  [7:0]    alu_x,
output   reg  [7:0]    alu_y,
output   reg  [7:0]    alu_a
 
);
 
reg  [7:0]    alu_op_a;
reg           alu_op_c;
 
 
wire          v_result;
reg           z_result;
reg           c_result;
 
wire          r_result;
wire [7:0]      result;
 
wire [7:0]     and_out;
wire [7:0]     orr_out;
wire [7:0]     eor_out;
 
 
wire [8:0]     a_sh_left;
wire [8:0]     a_sh_right;
wire [8:0]     b_sh_left;
wire [8:0]     b_sh_right;
 
 
always @ (*) begin
   case( alu_op_a_sel)
   `alu_op_a_00:   alu_op_a     = 8'h00;
   `alu_op_a_acc:  alu_op_a     = alu_a;
   `alu_op_a_x:    alu_op_a     = alu_x;
   `alu_op_a_y:    alu_op_a     = alu_y;
   `alu_op_a_ff:   alu_op_a     = 8'hff;
   `alu_op_a_psr:  alu_op_a     = alu_status;
   default:        alu_op_a     = 8'h00;
   endcase
   end
 
always @ (*) begin
   case( alu_op_c_sel)
   `alu_op_c_00:     alu_op_c    = 1'b0;
   `alu_op_c_01:     alu_op_c    = 1'b1;
   `alu_op_c_cin:    alu_op_c    = alu_status[`C];
   `alu_op_c_xx:     alu_op_c    = 1'b0;
   endcase
   end
 
 
`VARIANT`ALU_LOGIC
alu_logic (
    .alu_op_b_inv  ( alu_op_b_inv   ),
    .alu_op_a      ( alu_op_a       ),
    .alu_op_b      ( alu_op_b       ),
    .alu_op_c      ( alu_op_c       ),
    .result        (   result       ),
    .r_result      (                ),
    .c_result      ( r_result       ),
    .v_result      ( v_result       ),
    .and_out       ( and_out        ),
    .orr_out       ( orr_out        ),
    .eor_out       ( eor_out        ),
    .a_sh_left     ( a_sh_left      ),
    .a_sh_right    ( a_sh_right     ),
    .b_sh_left     ( b_sh_left      ),
    .b_sh_right    ( b_sh_right     )
 
);
 
 
 
 
 
 
 
 
 
 
always @ (posedge clk )
begin
     if (reset)
          begin
          alu_status[`N] <= 1'b0;
          alu_status[`V] <= 1'b0;
          alu_status[5]  <= 1'b1;
          alu_status[`B] <= 1'b0;
          alu_status[`D] <= 1'b0;
          alu_status[`I] <= 1'b0;
          alu_status[`Z] <= 1'b1;
          alu_status[`C] <= 1'b0;
          end
     else
     if (! (enable && alu_enable    ) )
        begin
        alu_status[7:6]    <= alu_status[7:6];
        alu_status[5:2]     <= alu_status[5:2];
        alu_status[1]     <= alu_status[1];
        alu_status[0]     <= alu_status[0];
        end
     else
     begin
     case (alu_status_update)
 
          `alu_status_update_none:
                     begin
                     alu_status[7:6]     <= alu_status[7:6];
                     end
 
 
           `alu_status_update_wr:
                     begin
                     alu_status[7]  <=  brn_enable[7]?brn_value[7]: alu_status[7];
                     alu_status[6]  <=  brn_enable[6]?brn_value[6]: alu_status[6];
                     end
 
           `alu_status_update_z67:
                     begin
                     alu_status[`N] <=  alu_op_b[`N];
                     alu_status[`V] <=  alu_op_b[`V];
                     end
 
           `alu_status_update_nz:
                     begin
                     alu_status[`N] <=  alu_result[7];
                     alu_status[`V] <=  alu_status[`V];
                     end
 
           `alu_status_update_nzc:
                     begin
                     alu_status[`N] <=  alu_result[7];
                     alu_status[`V] <=  alu_status[`V];
                     end
 
          `alu_status_update_nzcv:
                     begin
                     alu_status[`N] <=  alu_result[7];
                     alu_status[`V] <=  v_result;
                     end
 
 
 
            `alu_status_update_res:
                     begin
                     alu_status[7:6]     <=  psp_res[7:6];
                     end
 
           default:
                     begin
                     alu_status[`N] <=  alu_status[`N];
                     alu_status[`V] <=  alu_status[`V];
                     end
         endcase
 
 
     case (alu_status_update)
 
          `alu_status_update_none:
                     begin
                     alu_status[5:2]     <= alu_status[5:2];
                     end
 
 
           `alu_status_update_wr:
                     begin
                     alu_status[5]  <=  brn_enable[5]?brn_value[5]: alu_status[5];
                     alu_status[4]  <=  brn_enable[4]?brn_value[4]: alu_status[4];
                     alu_status[3]  <=  brn_enable[3]?brn_value[3]: alu_status[3];
                     alu_status[2]  <=  brn_enable[2]?brn_value[2]: alu_status[2];
                     end
 
           `alu_status_update_z67:
                     begin
                     alu_status[5]  <=  alu_status[5];
                     alu_status[`B] <=  alu_status[`B];
                     alu_status[`D] <=  alu_status[`D];
                     alu_status[`I] <=  alu_status[`I];
                     end
 
           `alu_status_update_nz:
                     begin
                     alu_status[5]  <=  alu_status[5];
                     alu_status[`B] <=  alu_status[`B];
                     alu_status[`D] <=  alu_status[`D];
                     alu_status[`I] <=  alu_status[`I];
                     end
 
           `alu_status_update_nzc:
                     begin
                     alu_status[5]  <=  alu_status[5];
                     alu_status[`B] <=  alu_status[`B];
                     alu_status[`D] <=  alu_status[`D];
                     alu_status[`I] <=  alu_status[`I];
                     end
 
          `alu_status_update_nzcv:
                     begin
                     alu_status[5]  <=  alu_status[5];
                     alu_status[`B] <=  alu_status[`B];
                     alu_status[`D] <=  alu_status[`D];
                     alu_status[`I] <=  alu_status[`I];
                     end
 
 
 
            `alu_status_update_res:
                     begin
                     alu_status[5:2]     <=  psp_res[5:2];
                     end
 
           default:
                     begin
                     alu_status[5]  <=  alu_status[5];
                     alu_status[`B] <=  alu_status[`B];
                     alu_status[`D] <=  alu_status[`D];
                     alu_status[`I] <=  alu_status[`I];
                     end
         endcase
 
 
     case (alu_status_update)
 
          `alu_status_update_none:
                     begin
                     alu_status[1]     <= alu_status[1];
                     end
 
           `alu_status_update_wr:
                     begin
                     alu_status[1]  <=  brn_enable[1]?brn_value[1]: alu_status[1];
                     end
 
           `alu_status_update_z67:
                     begin
                     alu_status[`Z] <=  z_result;
                     end
 
           `alu_status_update_nz:
                     begin
                     alu_status[`Z] <=  z_result;
                     end
 
           `alu_status_update_nzc:
                     begin
                     alu_status[`Z] <=  z_result;
                     end
 
          `alu_status_update_nzcv:
                     begin
                     alu_status[`Z] <=  z_result;
                     end
 
            `alu_status_update_res:
                     begin
                     alu_status[1]     <=  psp_res[1];
                     end
 
           default:
                     begin
                     alu_status[`Z] <=  alu_status[`Z];
                     end
     endcase // case (alu_status_update)
 
     case (alu_status_update)
 
          `alu_status_update_none:
                     begin
                     alu_status[0]     <= alu_status[0];
                     end
 
 
           `alu_status_update_wr:
                     begin
                     alu_status[0]  <=  brn_enable[0]?brn_value[0]: alu_status[0];
                     end
 
           `alu_status_update_z67:
                     begin
                     alu_status[`C] <=  alu_status[`C];
                     end
 
           `alu_status_update_nz:
                     begin
                     alu_status[`C] <=  alu_status[`C];
                     end
 
           `alu_status_update_nzc:
                     begin
                     alu_status[`C] <=  c_result;
                     end
 
          `alu_status_update_nzcv:
                     begin
                     alu_status[`C] <=  c_result;
                     end
 
 
 
            `alu_status_update_res:
                     begin
                     alu_status[0]     <=  psp_res[0];
                     end
 
           default:
                     begin
                     alu_status[`C] <=  alu_status[`C];
                     end
         endcase
 
        end
 
 
 
end
 
 
 
 
 
 
 
always @ (posedge clk )
begin
     if (reset)
          begin
          alu_a          <= 8'd0;
          end
     else
     if ( enable &&  alu_enable &&   (dest ==   `dest_alu_a))
          begin
          alu_a          <= alu_result[7:0];
          end
     else
          begin
          alu_a          <= alu_a;
          end
 
end
 
 
 
always @ (posedge clk )
begin
     if (reset)
          begin
          alu_x          <= 8'd0;
          end
     else
     if (!(enable &&  alu_enable))
          begin
          alu_x          <= alu_x;
          end
     else
     case (dest)
      `dest_alu_x:  alu_x          <= alu_result[7:0];
 
       default :
                   begin
                   alu_x          <= alu_x;
                   end
     endcase
 
end
 
 
 
 
always @ (posedge clk )
begin
     if (reset)
          begin
          alu_y          <= 8'd0;
          end
     else
     if (!(enable &&  alu_enable))
          begin
          alu_y          <= alu_y;
          end
     else
     case (dest)
      `dest_alu_y:  alu_y          <= alu_result[7:0];
 
       default :
                   begin
                   alu_y          <= alu_y;
                   end
     endcase
 
end
 
 
 
always @ (*)
        begin
        alu_result      = result[7:0];
        c_result        = r_result;
 
     if (dest ==   `dest_alu_a)
 
        case (alu_mode)
          `alu_mode_add:{c_result,alu_result[7:0]} = {r_result,result[7:0]};
          `alu_mode_and:{c_result,alu_result[7:0]} = {1'b0,and_out[7:0]};
          `alu_mode_orr:{c_result,alu_result[7:0]} = {1'b0,orr_out[7:0]};
          `alu_mode_eor:{c_result,alu_result[7:0]} = {1'b0,eor_out[7:0]};
          `alu_mode_sfl:{c_result,alu_result[7:0]} = a_sh_left;
          `alu_mode_sfr:{c_result,alu_result[7:0]} = a_sh_right;
                default:{c_result,alu_result[7:0]} = 9'b111111111;
 
       endcase
      else
        case (alu_mode)
          `alu_mode_add:{c_result,alu_result[7:0]} = {r_result,result[7:0]};
          `alu_mode_and:{c_result,alu_result[7:0]} = {1'b0,and_out[7:0]};
          `alu_mode_orr:{c_result,alu_result[7:0]} = {1'b0,orr_out[7:0]};
          `alu_mode_eor:{c_result,alu_result[7:0]} = {1'b0,eor_out[7:0]};
          `alu_mode_sfl:{c_result,alu_result[7:0]} = b_sh_left;
          `alu_mode_sfr:{c_result,alu_result[7:0]} = b_sh_right;
                default:{c_result,alu_result[7:0]} = 9'b111111111;
       endcase
 
       end
 
 
 
always@(*)
  begin
  z_result      = ~(|alu_result[7:0]);
  end
 
 
 
 
 
 
 
 
 
 
 
always@(*)     branch_inst = relative &&(   | (brn_enable & ( ~ (brn_value ^ alu_status))));
 
 
 
 
endmodule

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [core/] [rtl/] [verilog/] [alu] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2			module `VARIANT`ALU
3
4			`(`
5
6
7			`input wire clk,`
8			`input wire reset,`
9			`input wire enable,`
10
11			`input wire alu_enable,`
12
13			`input wire [7:0] alu_op_b,`
14			`input wire [7:0] psp_res,`
15
16			`input wire [7:0] brn_value,`
17			`input wire [7:0] brn_enable,`
18			`input wire [2:0] dest,`
19			`input wire relative,`
20			`input wire [2:0] alu_mode,`
21			`input wire [4:0] alu_status_update,`
22			`input wire [2:0] alu_op_a_sel,`
23			`input wire alu_op_b_inv,`
24			`input wire [1:0] alu_op_c_sel,`
25
26
27			`output reg branch_inst,`
28			`output reg [7:0] alu_result,`
29			`output reg [7:0] alu_status,`
30			`output reg [7:0] alu_x,`
31			`output reg [7:0] alu_y,`
32			`output reg [7:0] alu_a`
33
34			`);`
35
36			`reg [7:0] alu_op_a;`
37			`reg alu_op_c;`
38
39
40			`wire v_result;`
41			`reg z_result;`
42			`reg c_result;`
43
44			`wire r_result;`
45			`wire [7:0] result;`
46
47			`wire [7:0] and_out;`
48			`wire [7:0] orr_out;`
49			`wire [7:0] eor_out;`
50
51
52			`wire [8:0] a_sh_left;`
53			`wire [8:0] a_sh_right;`
54			`wire [8:0] b_sh_left;`
55			`wire [8:0] b_sh_right;`
56
57
58			`always @ (*) begin`
59			`case( alu_op_a_sel)`
60			`alu_op_a_00: alu_op_a = 8'h00;
61			`alu_op_a_acc: alu_op_a = alu_a;
62			`alu_op_a_x: alu_op_a = alu_x;
63			`alu_op_a_y: alu_op_a = alu_y;
64			`alu_op_a_ff: alu_op_a = 8'hff;
65			`alu_op_a_psr: alu_op_a = alu_status;
66			`default: alu_op_a = 8'h00;`
67			`endcase`
68			`end`
69
70			`always @ (*) begin`
71			`case( alu_op_c_sel)`
72			`alu_op_c_00: alu_op_c = 1'b0;
73			`alu_op_c_01: alu_op_c = 1'b1;
74			`alu_op_c_cin: alu_op_c = alu_status[`C];
75			`alu_op_c_xx: alu_op_c = 1'b0;
76			`endcase`
77			`end`
78
79
80			`VARIANT`ALU_LOGIC
81			`alu_logic (`
82			`.alu_op_b_inv ( alu_op_b_inv ),`
83			`.alu_op_a ( alu_op_a ),`
84			`.alu_op_b ( alu_op_b ),`
85			`.alu_op_c ( alu_op_c ),`
86			`.result ( result ),`
87			`.r_result ( ),`
88			`.c_result ( r_result ),`
89			`.v_result ( v_result ),`
90			`.and_out ( and_out ),`
91			`.orr_out ( orr_out ),`
92			`.eor_out ( eor_out ),`
93			`.a_sh_left ( a_sh_left ),`
94			`.a_sh_right ( a_sh_right ),`
95			`.b_sh_left ( b_sh_left ),`
96			`.b_sh_right ( b_sh_right )`
97
98			`);`
99
100
101
102
103
104
105
106
107
108
109			`always @ (posedge clk )`
110			`begin`
111			`if (reset)`
112			`begin`
113			alu_status[`N] <= 1'b0;
114			alu_status[`V] <= 1'b0;
115			`alu_status[5] <= 1'b1;`
116			alu_status[`B] <= 1'b0;
117			alu_status[`D] <= 1'b0;
118			alu_status[`I] <= 1'b0;
119			alu_status[`Z] <= 1'b1;
120			alu_status[`C] <= 1'b0;
121			`end`
122			`else`
123			`if (! (enable && alu_enable ) )`
124			`begin`
125			`alu_status[7:6] <= alu_status[7:6];`
126			`alu_status[5:2] <= alu_status[5:2];`
127			`alu_status[1] <= alu_status[1];`
128			`alu_status[0] <= alu_status[0];`
129			`end`
130			`else`
131			`begin`
132			`case (alu_status_update)`
133
134			`alu_status_update_none:
135			`begin`
136			`alu_status[7:6] <= alu_status[7:6];`
137			`end`
138
139
140			`alu_status_update_wr:
141			`begin`
142			`alu_status[7] <= brn_enable[7]?brn_value[7]: alu_status[7];`
143			`alu_status[6] <= brn_enable[6]?brn_value[6]: alu_status[6];`
144			`end`
145
146			`alu_status_update_z67:
147			`begin`
148			alu_status[`N] <= alu_op_b[`N];
149			alu_status[`V] <= alu_op_b[`V];
150			`end`
151
152			`alu_status_update_nz:
153			`begin`
154			alu_status[`N] <= alu_result[7];
155			alu_status[`V] <= alu_status[`V];
156			`end`
157
158			`alu_status_update_nzc:
159			`begin`
160			alu_status[`N] <= alu_result[7];
161			alu_status[`V] <= alu_status[`V];
162			`end`
163
164			`alu_status_update_nzcv:
165			`begin`
166			alu_status[`N] <= alu_result[7];
167			alu_status[`V] <= v_result;
168			`end`
169
170
171
172			`alu_status_update_res:
173			`begin`
174			`alu_status[7:6] <= psp_res[7:6];`
175			`end`
176
177			`default:`
178			`begin`
179			alu_status[`N] <= alu_status[`N];
180			alu_status[`V] <= alu_status[`V];
181			`end`
182			`endcase`
183
184
185			`case (alu_status_update)`
186
187			`alu_status_update_none:
188			`begin`
189			`alu_status[5:2] <= alu_status[5:2];`
190			`end`
191
192
193			`alu_status_update_wr:
194			`begin`
195			`alu_status[5] <= brn_enable[5]?brn_value[5]: alu_status[5];`
196			`alu_status[4] <= brn_enable[4]?brn_value[4]: alu_status[4];`
197			`alu_status[3] <= brn_enable[3]?brn_value[3]: alu_status[3];`
198			`alu_status[2] <= brn_enable[2]?brn_value[2]: alu_status[2];`
199			`end`
200
201			`alu_status_update_z67:
202			`begin`
203			`alu_status[5] <= alu_status[5];`
204			alu_status[`B] <= alu_status[`B];
205			alu_status[`D] <= alu_status[`D];
206			alu_status[`I] <= alu_status[`I];
207			`end`
208
209			`alu_status_update_nz:
210			`begin`
211			`alu_status[5] <= alu_status[5];`
212			alu_status[`B] <= alu_status[`B];
213			alu_status[`D] <= alu_status[`D];
214			alu_status[`I] <= alu_status[`I];
215			`end`
216
217			`alu_status_update_nzc:
218			`begin`
219			`alu_status[5] <= alu_status[5];`
220			alu_status[`B] <= alu_status[`B];
221			alu_status[`D] <= alu_status[`D];
222			alu_status[`I] <= alu_status[`I];
223			`end`
224
225			`alu_status_update_nzcv:
226			`begin`
227			`alu_status[5] <= alu_status[5];`
228			alu_status[`B] <= alu_status[`B];
229			alu_status[`D] <= alu_status[`D];
230			alu_status[`I] <= alu_status[`I];
231			`end`
232
233
234
235			`alu_status_update_res:
236			`begin`
237			`alu_status[5:2] <= psp_res[5:2];`
238			`end`
239
240			`default:`
241			`begin`
242			`alu_status[5] <= alu_status[5];`
243			alu_status[`B] <= alu_status[`B];
244			alu_status[`D] <= alu_status[`D];
245			alu_status[`I] <= alu_status[`I];
246			`end`
247			`endcase`
248
249
250			`case (alu_status_update)`
251
252			`alu_status_update_none:
253			`begin`
254			`alu_status[1] <= alu_status[1];`
255			`end`
256
257			`alu_status_update_wr:
258			`begin`
259			`alu_status[1] <= brn_enable[1]?brn_value[1]: alu_status[1];`
260			`end`
261
262			`alu_status_update_z67:
263			`begin`
264			alu_status[`Z] <= z_result;
265			`end`
266
267			`alu_status_update_nz:
268			`begin`
269			alu_status[`Z] <= z_result;
270			`end`
271
272			`alu_status_update_nzc:
273			`begin`
274			alu_status[`Z] <= z_result;
275			`end`
276
277			`alu_status_update_nzcv:
278			`begin`
279			alu_status[`Z] <= z_result;
280			`end`
281
282			`alu_status_update_res:
283			`begin`
284			`alu_status[1] <= psp_res[1];`
285			`end`
286
287			`default:`
288			`begin`
289			alu_status[`Z] <= alu_status[`Z];
290			`end`
291			`endcase // case (alu_status_update)`
292
293			`case (alu_status_update)`
294
295			`alu_status_update_none:
296			`begin`
297			`alu_status[0] <= alu_status[0];`
298			`end`
299
300
301			`alu_status_update_wr:
302			`begin`
303			`alu_status[0] <= brn_enable[0]?brn_value[0]: alu_status[0];`
304			`end`
305
306			`alu_status_update_z67:
307			`begin`
308			alu_status[`C] <= alu_status[`C];
309			`end`
310
311			`alu_status_update_nz:
312			`begin`
313			alu_status[`C] <= alu_status[`C];
314			`end`
315
316			`alu_status_update_nzc:
317			`begin`
318			alu_status[`C] <= c_result;
319			`end`
320
321			`alu_status_update_nzcv:
322			`begin`
323			alu_status[`C] <= c_result;
324			`end`
325
326
327
328			`alu_status_update_res:
329			`begin`
330			`alu_status[0] <= psp_res[0];`
331			`end`
332
333			`default:`
334			`begin`
335			alu_status[`C] <= alu_status[`C];
336			`end`
337			`endcase`
338
339			`end`
340
341
342
343			`end`
344
345
346
347
348
349
350
351			`always @ (posedge clk )`
352			`begin`
353			`if (reset)`
354			`begin`
355			`alu_a <= 8'd0;`
356			`end`
357			`else`
358			if ( enable && alu_enable && (dest == `dest_alu_a))
359			`begin`
360			`alu_a <= alu_result[7:0];`
361			`end`
362			`else`
363			`begin`
364			`alu_a <= alu_a;`
365			`end`
366
367			`end`
368
369
370
371			`always @ (posedge clk )`
372			`begin`
373			`if (reset)`
374			`begin`
375			`alu_x <= 8'd0;`
376			`end`
377			`else`
378			`if (!(enable && alu_enable))`
379			`begin`
380			`alu_x <= alu_x;`
381			`end`
382			`else`
383			`case (dest)`
384			`dest_alu_x: alu_x <= alu_result[7:0];
385
386			`default :`
387			`begin`
388			`alu_x <= alu_x;`
389			`end`
390			`endcase`
391
392			`end`
393
394
395
396
397			`always @ (posedge clk )`
398			`begin`
399			`if (reset)`
400			`begin`
401			`alu_y <= 8'd0;`
402			`end`
403			`else`
404			`if (!(enable && alu_enable))`
405			`begin`
406			`alu_y <= alu_y;`
407			`end`
408			`else`
409			`case (dest)`
410			`dest_alu_y: alu_y <= alu_result[7:0];
411
412			`default :`
413			`begin`
414			`alu_y <= alu_y;`
415			`end`
416			`endcase`
417
418			`end`
419
420
421
422			`always @ (*)`
423			`begin`
424			`alu_result = result[7:0];`
425			`c_result = r_result;`
426
427			if (dest == `dest_alu_a)
428
429			`case (alu_mode)`
430			`alu_mode_add:{c_result,alu_result[7:0]} = {r_result,result[7:0]};
431			`alu_mode_and:{c_result,alu_result[7:0]} = {1'b0,and_out[7:0]};
432			`alu_mode_orr:{c_result,alu_result[7:0]} = {1'b0,orr_out[7:0]};
433			`alu_mode_eor:{c_result,alu_result[7:0]} = {1'b0,eor_out[7:0]};
434			`alu_mode_sfl:{c_result,alu_result[7:0]} = a_sh_left;
435			`alu_mode_sfr:{c_result,alu_result[7:0]} = a_sh_right;
436			`default:{c_result,alu_result[7:0]} = 9'b111111111;`
437
438			`endcase`
439			`else`
440			`case (alu_mode)`
441			`alu_mode_add:{c_result,alu_result[7:0]} = {r_result,result[7:0]};
442			`alu_mode_and:{c_result,alu_result[7:0]} = {1'b0,and_out[7:0]};
443			`alu_mode_orr:{c_result,alu_result[7:0]} = {1'b0,orr_out[7:0]};
444			`alu_mode_eor:{c_result,alu_result[7:0]} = {1'b0,eor_out[7:0]};
445			`alu_mode_sfl:{c_result,alu_result[7:0]} = b_sh_left;
446			`alu_mode_sfr:{c_result,alu_result[7:0]} = b_sh_right;
447			`default:{c_result,alu_result[7:0]} = 9'b111111111;`
448			`endcase`
449
450			`end`
451
452
453
454			`always@(*)`
455			`begin`
456			`z_result = ~(\|alu_result[7:0]);`
457			`end`
458
459
460
461
462
463
464
465
466
467
468
469			`always@(*) branch_inst = relative &&( \| (brn_enable & ( ~ (brn_value ^ alu_status))));`
470
471
472
473
474			`endmodule`