URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [core/] [rtl/] [verilog/] [alu] - Blame information for rev 134

Details | Compare with Previous | View Log


 
module `VARIANT`ALU
 
(
 
 
input   wire           clk,
input   wire           reset,
input   wire           enable,
 
input   wire           alu_enable,
 
input   wire  [7:0]    alu_op_b,
input   wire  [7:0]    psp_res,
 
input   wire  [7:0]    brn_value,
input   wire  [7:0]    brn_enable,
input   wire  [2:0]    dest,
input   wire           relative,
input   wire  [2:0]    alu_mode,
input   wire  [4:0]    alu_status_update,
input   wire  [2:0]    alu_op_a_sel,
input   wire           alu_op_b_inv,
input   wire  [1:0]    alu_op_c_sel,
 
 
output   reg           branch_inst,
output   reg  [7:0]    alu_result,
output   reg  [7:0]    alu_status,
output   reg  [7:0]    alu_x,
output   reg  [7:0]    alu_y,
output   reg  [7:0]    alu_a
 
);
 
reg  [7:0]    alu_op_a;
reg           alu_op_c;
 
 
wire          v_result;
reg           z_result;
reg           c_result;
 
wire          r_result;
wire          r_result_nc;
wire [7:0]      result;
 
wire [7:0]     and_out;
wire [7:0]     orr_out;
wire [7:0]     eor_out;
 
 
wire [8:0]     a_sh_left;
wire [8:0]     a_sh_right;
wire [8:0]     b_sh_left;
wire [8:0]     b_sh_right;
 
 
always @ (*) begin
   case( alu_op_a_sel)
   `alu_op_a_00:   alu_op_a     = 8'h00;
   `alu_op_a_acc:  alu_op_a     = alu_a;
   `alu_op_a_x:    alu_op_a     = alu_x;
   `alu_op_a_y:    alu_op_a     = alu_y;
   `alu_op_a_ff:   alu_op_a     = 8'hff;
   `alu_op_a_psr:  alu_op_a     = alu_status;
   default:        alu_op_a     = 8'h00;
   endcase
   end
 
always @ (*) begin
   case( alu_op_c_sel)
   `alu_op_c_00:     alu_op_c    = 1'b0;
   `alu_op_c_01:     alu_op_c    = 1'b1;
   `alu_op_c_cin:    alu_op_c    = alu_status[`C];
   `alu_op_c_xx:     alu_op_c    = 1'b0;
   endcase
   end
 
 
`VARIANT`ALU_LOGIC
alu_logic (
    .alu_op_b_inv  ( alu_op_b_inv   ),
    .alu_op_a      ( alu_op_a       ),
    .alu_op_b      ( alu_op_b       ),
    .alu_op_c      ( alu_op_c       ),
    .result        (   result       ),
    .r_result      ( r_result_nc    ),
    .c_result      ( r_result       ),
    .v_result      ( v_result       ),
    .and_out       ( and_out        ),
    .orr_out       ( orr_out        ),
    .eor_out       ( eor_out        ),
    .a_sh_left     ( a_sh_left      ),
    .a_sh_right    ( a_sh_right     ),
    .b_sh_left     ( b_sh_left      ),
    .b_sh_right    ( b_sh_right     )
 
);
 
 
 
 
 
 
 
 
 
 
always @ (posedge clk )
begin
     if (reset)
          begin
          alu_status[`N] <= 1'b0;
          alu_status[`V] <= 1'b0;
          alu_status[5]  <= 1'b1;
          alu_status[`B] <= 1'b0;
          alu_status[`D] <= 1'b0;
          alu_status[`I] <= 1'b0;
          alu_status[`Z] <= 1'b1;
          alu_status[`C] <= 1'b0;
          end
     else
     if (! (enable && alu_enable    ) )
        begin
        alu_status[7:6]    <= alu_status[7:6];
        alu_status[5:2]     <= alu_status[5:2];
        alu_status[1]     <= alu_status[1];
        alu_status[0]     <= alu_status[0];
        end
     else
     begin
     case (alu_status_update)
 
          `alu_status_update_none:
                     begin
                     alu_status[7:6]     <= alu_status[7:6];
                     end
 
 
           `alu_status_update_wr:
                     begin
                     alu_status[7]  <=  brn_enable[7]?brn_value[7]: alu_status[7];
                     alu_status[6]  <=  brn_enable[6]?brn_value[6]: alu_status[6];
                     end
 
           `alu_status_update_z67:
                     begin
                     alu_status[`N] <=  alu_op_b[`N];
                     alu_status[`V] <=  alu_op_b[`V];
                     end
 
           `alu_status_update_nz:
                     begin
                     alu_status[`N] <=  alu_result[7];
                     alu_status[`V] <=  alu_status[`V];
                     end
 
           `alu_status_update_nzc:
                     begin
                     alu_status[`N] <=  alu_result[7];
                     alu_status[`V] <=  alu_status[`V];
                     end
 
          `alu_status_update_nzcv:
                     begin
                     alu_status[`N] <=  alu_result[7];
                     alu_status[`V] <=  v_result;
                     end
 
 
 
            `alu_status_update_res:
                     begin
                     alu_status[7:6]     <=  psp_res[7:6];
                     end
 
           default:
                     begin
                     alu_status[`N] <=  alu_status[`N];
                     alu_status[`V] <=  alu_status[`V];
                     end
         endcase
 
 
     case (alu_status_update)
 
          `alu_status_update_none:
                     begin
                     alu_status[5:2]     <= alu_status[5:2];
                     end
 
 
           `alu_status_update_wr:
                     begin
                     alu_status[5]  <=  brn_enable[5]?brn_value[5]: alu_status[5];
                     alu_status[4]  <=  brn_enable[4]?brn_value[4]: alu_status[4];
                     alu_status[3]  <=  brn_enable[3]?brn_value[3]: alu_status[3];
                     alu_status[2]  <=  brn_enable[2]?brn_value[2]: alu_status[2];
                     end
 
           `alu_status_update_z67:
                     begin
                     alu_status[5]  <=  alu_status[5];
                     alu_status[`B] <=  alu_status[`B];
                     alu_status[`D] <=  alu_status[`D];
                     alu_status[`I] <=  alu_status[`I];
                     end
 
           `alu_status_update_nz:
                     begin
                     alu_status[5]  <=  alu_status[5];
                     alu_status[`B] <=  alu_status[`B];
                     alu_status[`D] <=  alu_status[`D];
                     alu_status[`I] <=  alu_status[`I];
                     end
 
           `alu_status_update_nzc:
                     begin
                     alu_status[5]  <=  alu_status[5];
                     alu_status[`B] <=  alu_status[`B];
                     alu_status[`D] <=  alu_status[`D];
                     alu_status[`I] <=  alu_status[`I];
                     end
 
          `alu_status_update_nzcv:
                     begin
                     alu_status[5]  <=  alu_status[5];
                     alu_status[`B] <=  alu_status[`B];
                     alu_status[`D] <=  alu_status[`D];
                     alu_status[`I] <=  alu_status[`I];
                     end
 
 
 
            `alu_status_update_res:
                     begin
                     alu_status[5:2]     <=  psp_res[5:2];
                     end
 
           default:
                     begin
                     alu_status[5]  <=  alu_status[5];
                     alu_status[`B] <=  alu_status[`B];
                     alu_status[`D] <=  alu_status[`D];
                     alu_status[`I] <=  alu_status[`I];
                     end
         endcase
 
 
     case (alu_status_update)
 
          `alu_status_update_none:
                     begin
                     alu_status[1]     <= alu_status[1];
                     end
 
           `alu_status_update_wr:
                     begin
                     alu_status[1]  <=  brn_enable[1]?brn_value[1]: alu_status[1];
                     end
 
           `alu_status_update_z67:
                     begin
                     alu_status[`Z] <=  z_result;
                     end
 
           `alu_status_update_nz:
                     begin
                     alu_status[`Z] <=  z_result;
                     end
 
           `alu_status_update_nzc:
                     begin
                     alu_status[`Z] <=  z_result;
                     end
 
          `alu_status_update_nzcv:
                     begin
                     alu_status[`Z] <=  z_result;
                     end
 
            `alu_status_update_res:
                     begin
                     alu_status[1]     <=  psp_res[1];
                     end
 
           default:
                     begin
                     alu_status[`Z] <=  alu_status[`Z];
                     end
     endcase // case (alu_status_update)
 
     case (alu_status_update)
 
          `alu_status_update_none:
                     begin
                     alu_status[0]     <= alu_status[0];
                     end
 
 
           `alu_status_update_wr:
                     begin
                     alu_status[0]  <=  brn_enable[0]?brn_value[0]: alu_status[0];
                     end
 
           `alu_status_update_z67:
                     begin
                     alu_status[`C] <=  alu_status[`C];
                     end
 
           `alu_status_update_nz:
                     begin
                     alu_status[`C] <=  alu_status[`C];
                     end
 
           `alu_status_update_nzc:
                     begin
                     alu_status[`C] <=  c_result;
                     end
 
          `alu_status_update_nzcv:
                     begin
                     alu_status[`C] <=  c_result;
                     end
 
 
 
            `alu_status_update_res:
                     begin
                     alu_status[0]     <=  psp_res[0];
                     end
 
           default:
                     begin
                     alu_status[`C] <=  alu_status[`C];
                     end
         endcase
 
        end
 
 
 
end
 
 
 
 
 
 
 
always @ (posedge clk )
begin
     if (reset)
          begin
          alu_a          <= 8'd0;
          end
     else
     if ( enable &&  alu_enable &&   (dest ==   `dest_alu_a))
          begin
          alu_a          <= alu_result[7:0];
          end
     else
          begin
          alu_a          <= alu_a;
          end
 
end
 
 
 
always @ (posedge clk )
begin
     if (reset)
          begin
          alu_x          <= 8'd0;
          end
     else
     if (!(enable &&  alu_enable))
          begin
          alu_x          <= alu_x;
          end
     else
     case (dest)
      `dest_alu_x:  alu_x          <= alu_result[7:0];
 
       default :
                   begin
                   alu_x          <= alu_x;
                   end
     endcase
 
end
 
 
 
 
always @ (posedge clk )
begin
     if (reset)
          begin
          alu_y          <= 8'd0;
          end
     else
     if (!(enable &&  alu_enable))
          begin
          alu_y          <= alu_y;
          end
     else
     case (dest)
      `dest_alu_y:  alu_y          <= alu_result[7:0];
 
       default :
                   begin
                   alu_y          <= alu_y;
                   end
     endcase
 
end
 
 
 
always @ (*)
        begin
        alu_result      = result[7:0];
        c_result        = r_result;
 
     if (dest ==   `dest_alu_a)
 
        case (alu_mode)
          `alu_mode_add:{c_result,alu_result[7:0]} = {r_result,result[7:0]};
          `alu_mode_and:{c_result,alu_result[7:0]} = {1'b0,and_out[7:0]};
          `alu_mode_orr:{c_result,alu_result[7:0]} = {1'b0,orr_out[7:0]};
          `alu_mode_eor:{c_result,alu_result[7:0]} = {1'b0,eor_out[7:0]};
          `alu_mode_sfl:{c_result,alu_result[7:0]} = a_sh_left;
          `alu_mode_sfr:{c_result,alu_result[7:0]} = a_sh_right;
                default:{c_result,alu_result[7:0]} = 9'b111111111;
 
       endcase
      else
        case (alu_mode)
          `alu_mode_add:{c_result,alu_result[7:0]} = {r_result,result[7:0]};
          `alu_mode_and:{c_result,alu_result[7:0]} = {1'b0,and_out[7:0]};
          `alu_mode_orr:{c_result,alu_result[7:0]} = {1'b0,orr_out[7:0]};
          `alu_mode_eor:{c_result,alu_result[7:0]} = {1'b0,eor_out[7:0]};
          `alu_mode_sfl:{c_result,alu_result[7:0]} = b_sh_left;
          `alu_mode_sfr:{c_result,alu_result[7:0]} = b_sh_right;
                default:{c_result,alu_result[7:0]} = 9'b111111111;
       endcase
 
       end
 
 
 
always@(*)
  begin
  z_result      = ~(|alu_result[7:0]);
  end
 
 
 
 
 
 
 
 
 
 
 
always@(*)     branch_inst = relative &&(   | (brn_enable & ( ~ (brn_value ^ alu_status))));
 
 
 
 
endmodule

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [core/] [rtl/] [verilog/] [alu] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2			module `VARIANT`ALU
3
4			`(`
5
6
7			`input wire clk,`
8			`input wire reset,`
9			`input wire enable,`
10
11			`input wire alu_enable,`
12
13			`input wire [7:0] alu_op_b,`
14			`input wire [7:0] psp_res,`
15
16			`input wire [7:0] brn_value,`
17			`input wire [7:0] brn_enable,`
18			`input wire [2:0] dest,`
19			`input wire relative,`
20			`input wire [2:0] alu_mode,`
21			`input wire [4:0] alu_status_update,`
22			`input wire [2:0] alu_op_a_sel,`
23			`input wire alu_op_b_inv,`
24			`input wire [1:0] alu_op_c_sel,`
25
26
27			`output reg branch_inst,`
28			`output reg [7:0] alu_result,`
29			`output reg [7:0] alu_status,`
30			`output reg [7:0] alu_x,`
31			`output reg [7:0] alu_y,`
32			`output reg [7:0] alu_a`
33
34			`);`
35
36			`reg [7:0] alu_op_a;`
37			`reg alu_op_c;`
38
39
40			`wire v_result;`
41			`reg z_result;`
42			`reg c_result;`
43
44			`wire r_result;`
45	134	jt_eaton	`wire r_result_nc;`
46	131	jt_eaton	`wire [7:0] result;`
47
48			`wire [7:0] and_out;`
49			`wire [7:0] orr_out;`
50			`wire [7:0] eor_out;`
51
52
53			`wire [8:0] a_sh_left;`
54			`wire [8:0] a_sh_right;`
55			`wire [8:0] b_sh_left;`
56			`wire [8:0] b_sh_right;`
57
58
59			`always @ (*) begin`
60			`case( alu_op_a_sel)`
61			`alu_op_a_00: alu_op_a = 8'h00;
62			`alu_op_a_acc: alu_op_a = alu_a;
63			`alu_op_a_x: alu_op_a = alu_x;
64			`alu_op_a_y: alu_op_a = alu_y;
65			`alu_op_a_ff: alu_op_a = 8'hff;
66			`alu_op_a_psr: alu_op_a = alu_status;
67			`default: alu_op_a = 8'h00;`
68			`endcase`
69			`end`
70
71			`always @ (*) begin`
72			`case( alu_op_c_sel)`
73			`alu_op_c_00: alu_op_c = 1'b0;
74			`alu_op_c_01: alu_op_c = 1'b1;
75			`alu_op_c_cin: alu_op_c = alu_status[`C];
76			`alu_op_c_xx: alu_op_c = 1'b0;
77			`endcase`
78			`end`
79
80
81			`VARIANT`ALU_LOGIC
82			`alu_logic (`
83			`.alu_op_b_inv ( alu_op_b_inv ),`
84			`.alu_op_a ( alu_op_a ),`
85			`.alu_op_b ( alu_op_b ),`
86			`.alu_op_c ( alu_op_c ),`
87			`.result ( result ),`
88	134	jt_eaton	`.r_result ( r_result_nc ),`
89	131	jt_eaton	`.c_result ( r_result ),`
90			`.v_result ( v_result ),`
91			`.and_out ( and_out ),`
92			`.orr_out ( orr_out ),`
93			`.eor_out ( eor_out ),`
94			`.a_sh_left ( a_sh_left ),`
95			`.a_sh_right ( a_sh_right ),`
96			`.b_sh_left ( b_sh_left ),`
97			`.b_sh_right ( b_sh_right )`
98
99			`);`
100
101
102
103
104
105
106
107
108
109
110			`always @ (posedge clk )`
111			`begin`
112			`if (reset)`
113			`begin`
114			alu_status[`N] <= 1'b0;
115			alu_status[`V] <= 1'b0;
116			`alu_status[5] <= 1'b1;`
117			alu_status[`B] <= 1'b0;
118			alu_status[`D] <= 1'b0;
119			alu_status[`I] <= 1'b0;
120			alu_status[`Z] <= 1'b1;
121			alu_status[`C] <= 1'b0;
122			`end`
123			`else`
124			`if (! (enable && alu_enable ) )`
125			`begin`
126			`alu_status[7:6] <= alu_status[7:6];`
127			`alu_status[5:2] <= alu_status[5:2];`
128			`alu_status[1] <= alu_status[1];`
129			`alu_status[0] <= alu_status[0];`
130			`end`
131			`else`
132			`begin`
133			`case (alu_status_update)`
134
135			`alu_status_update_none:
136			`begin`
137			`alu_status[7:6] <= alu_status[7:6];`
138			`end`
139
140
141			`alu_status_update_wr:
142			`begin`
143			`alu_status[7] <= brn_enable[7]?brn_value[7]: alu_status[7];`
144			`alu_status[6] <= brn_enable[6]?brn_value[6]: alu_status[6];`
145			`end`
146
147			`alu_status_update_z67:
148			`begin`
149			alu_status[`N] <= alu_op_b[`N];
150			alu_status[`V] <= alu_op_b[`V];
151			`end`
152
153			`alu_status_update_nz:
154			`begin`
155			alu_status[`N] <= alu_result[7];
156			alu_status[`V] <= alu_status[`V];
157			`end`
158
159			`alu_status_update_nzc:
160			`begin`
161			alu_status[`N] <= alu_result[7];
162			alu_status[`V] <= alu_status[`V];
163			`end`
164
165			`alu_status_update_nzcv:
166			`begin`
167			alu_status[`N] <= alu_result[7];
168			alu_status[`V] <= v_result;
169			`end`
170
171
172
173			`alu_status_update_res:
174			`begin`
175			`alu_status[7:6] <= psp_res[7:6];`
176			`end`
177
178			`default:`
179			`begin`
180			alu_status[`N] <= alu_status[`N];
181			alu_status[`V] <= alu_status[`V];
182			`end`
183			`endcase`
184
185
186			`case (alu_status_update)`
187
188			`alu_status_update_none:
189			`begin`
190			`alu_status[5:2] <= alu_status[5:2];`
191			`end`
192
193
194			`alu_status_update_wr:
195			`begin`
196			`alu_status[5] <= brn_enable[5]?brn_value[5]: alu_status[5];`
197			`alu_status[4] <= brn_enable[4]?brn_value[4]: alu_status[4];`
198			`alu_status[3] <= brn_enable[3]?brn_value[3]: alu_status[3];`
199			`alu_status[2] <= brn_enable[2]?brn_value[2]: alu_status[2];`
200			`end`
201
202			`alu_status_update_z67:
203			`begin`
204			`alu_status[5] <= alu_status[5];`
205			alu_status[`B] <= alu_status[`B];
206			alu_status[`D] <= alu_status[`D];
207			alu_status[`I] <= alu_status[`I];
208			`end`
209
210			`alu_status_update_nz:
211			`begin`
212			`alu_status[5] <= alu_status[5];`
213			alu_status[`B] <= alu_status[`B];
214			alu_status[`D] <= alu_status[`D];
215			alu_status[`I] <= alu_status[`I];
216			`end`
217
218			`alu_status_update_nzc:
219			`begin`
220			`alu_status[5] <= alu_status[5];`
221			alu_status[`B] <= alu_status[`B];
222			alu_status[`D] <= alu_status[`D];
223			alu_status[`I] <= alu_status[`I];
224			`end`
225
226			`alu_status_update_nzcv:
227			`begin`
228			`alu_status[5] <= alu_status[5];`
229			alu_status[`B] <= alu_status[`B];
230			alu_status[`D] <= alu_status[`D];
231			alu_status[`I] <= alu_status[`I];
232			`end`
233
234
235
236			`alu_status_update_res:
237			`begin`
238			`alu_status[5:2] <= psp_res[5:2];`
239			`end`
240
241			`default:`
242			`begin`
243			`alu_status[5] <= alu_status[5];`
244			alu_status[`B] <= alu_status[`B];
245			alu_status[`D] <= alu_status[`D];
246			alu_status[`I] <= alu_status[`I];
247			`end`
248			`endcase`
249
250
251			`case (alu_status_update)`
252
253			`alu_status_update_none:
254			`begin`
255			`alu_status[1] <= alu_status[1];`
256			`end`
257
258			`alu_status_update_wr:
259			`begin`
260			`alu_status[1] <= brn_enable[1]?brn_value[1]: alu_status[1];`
261			`end`
262
263			`alu_status_update_z67:
264			`begin`
265			alu_status[`Z] <= z_result;
266			`end`
267
268			`alu_status_update_nz:
269			`begin`
270			alu_status[`Z] <= z_result;
271			`end`
272
273			`alu_status_update_nzc:
274			`begin`
275			alu_status[`Z] <= z_result;
276			`end`
277
278			`alu_status_update_nzcv:
279			`begin`
280			alu_status[`Z] <= z_result;
281			`end`
282
283			`alu_status_update_res:
284			`begin`
285			`alu_status[1] <= psp_res[1];`
286			`end`
287
288			`default:`
289			`begin`
290			alu_status[`Z] <= alu_status[`Z];
291			`end`
292			`endcase // case (alu_status_update)`
293
294			`case (alu_status_update)`
295
296			`alu_status_update_none:
297			`begin`
298			`alu_status[0] <= alu_status[0];`
299			`end`
300
301
302			`alu_status_update_wr:
303			`begin`
304			`alu_status[0] <= brn_enable[0]?brn_value[0]: alu_status[0];`
305			`end`
306
307			`alu_status_update_z67:
308			`begin`
309			alu_status[`C] <= alu_status[`C];
310			`end`
311
312			`alu_status_update_nz:
313			`begin`
314			alu_status[`C] <= alu_status[`C];
315			`end`
316
317			`alu_status_update_nzc:
318			`begin`
319			alu_status[`C] <= c_result;
320			`end`
321
322			`alu_status_update_nzcv:
323			`begin`
324			alu_status[`C] <= c_result;
325			`end`
326
327
328
329			`alu_status_update_res:
330			`begin`
331			`alu_status[0] <= psp_res[0];`
332			`end`
333
334			`default:`
335			`begin`
336			alu_status[`C] <= alu_status[`C];
337			`end`
338			`endcase`
339
340			`end`
341
342
343
344			`end`
345
346
347
348
349
350
351
352			`always @ (posedge clk )`
353			`begin`
354			`if (reset)`
355			`begin`
356			`alu_a <= 8'd0;`
357			`end`
358			`else`
359			if ( enable && alu_enable && (dest == `dest_alu_a))
360			`begin`
361			`alu_a <= alu_result[7:0];`
362			`end`
363			`else`
364			`begin`
365			`alu_a <= alu_a;`
366			`end`
367
368			`end`
369
370
371
372			`always @ (posedge clk )`
373			`begin`
374			`if (reset)`
375			`begin`
376			`alu_x <= 8'd0;`
377			`end`
378			`else`
379			`if (!(enable && alu_enable))`
380			`begin`
381			`alu_x <= alu_x;`
382			`end`
383			`else`
384			`case (dest)`
385			`dest_alu_x: alu_x <= alu_result[7:0];
386
387			`default :`
388			`begin`
389			`alu_x <= alu_x;`
390			`end`
391			`endcase`
392
393			`end`
394
395
396
397
398			`always @ (posedge clk )`
399			`begin`
400			`if (reset)`
401			`begin`
402			`alu_y <= 8'd0;`
403			`end`
404			`else`
405			`if (!(enable && alu_enable))`
406			`begin`
407			`alu_y <= alu_y;`
408			`end`
409			`else`
410			`case (dest)`
411			`dest_alu_y: alu_y <= alu_result[7:0];
412
413			`default :`
414			`begin`
415			`alu_y <= alu_y;`
416			`end`
417			`endcase`
418
419			`end`
420
421
422
423			`always @ (*)`
424			`begin`
425			`alu_result = result[7:0];`
426			`c_result = r_result;`
427
428			if (dest == `dest_alu_a)
429
430			`case (alu_mode)`
431			`alu_mode_add:{c_result,alu_result[7:0]} = {r_result,result[7:0]};
432			`alu_mode_and:{c_result,alu_result[7:0]} = {1'b0,and_out[7:0]};
433			`alu_mode_orr:{c_result,alu_result[7:0]} = {1'b0,orr_out[7:0]};
434			`alu_mode_eor:{c_result,alu_result[7:0]} = {1'b0,eor_out[7:0]};
435			`alu_mode_sfl:{c_result,alu_result[7:0]} = a_sh_left;
436			`alu_mode_sfr:{c_result,alu_result[7:0]} = a_sh_right;
437			`default:{c_result,alu_result[7:0]} = 9'b111111111;`
438
439			`endcase`
440			`else`
441			`case (alu_mode)`
442			`alu_mode_add:{c_result,alu_result[7:0]} = {r_result,result[7:0]};
443			`alu_mode_and:{c_result,alu_result[7:0]} = {1'b0,and_out[7:0]};
444			`alu_mode_orr:{c_result,alu_result[7:0]} = {1'b0,orr_out[7:0]};
445			`alu_mode_eor:{c_result,alu_result[7:0]} = {1'b0,eor_out[7:0]};
446			`alu_mode_sfl:{c_result,alu_result[7:0]} = b_sh_left;
447			`alu_mode_sfr:{c_result,alu_result[7:0]} = b_sh_right;
448			`default:{c_result,alu_result[7:0]} = 9'b111111111;`
449			`endcase`
450
451			`end`
452
453
454
455			`always@(*)`
456			`begin`
457			`z_result = ~(\|alu_result[7:0]);`
458			`end`
459
460
461
462
463
464
465
466
467
468
469
470			`always@(*) branch_inst = relative &&( \| (brn_enable & ( ~ (brn_value ^ alu_status))));`
471
472
473
474
475			`endmodule`