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module  `VARIANT`CONTROL
 
#( parameter BOOT_VEC =8'hfc,
   parameter STATE_SIZE=3
)
(
input wire                    clk,
input wire                    reset,
input wire                    enable,
input wire                    nmi,
input wire [7:0]              vec_int,
input wire                    invalid,
input wire                    run_status,
input wire                    irq_status,
input wire                    brk_status,
input wire [STATE_SIZE:0]    state,
input wire   [2:0]            ctrl,
input wire   [7:0]            ir,
input wire  [15:0]            address,
input wire                    branch_inst,
 
output reg   [7:0]            vector,
output reg   [1:0]            cmd,
output reg                    core_reset
);
 
 
reg nmi_taken   ;
 
always @ (posedge clk )
begin
     if (reset)
      begin
      nmi_taken      <= 1'b0;
      end
     else
     if (!nmi)
      begin
      nmi_taken      <= 1'b0;
      end
     else
     if (ir == `RTI_IMP)
      begin
      nmi_taken      <= 1'b0;
      end
     else
     if (nmi && (state == `INT_1))
      begin
      nmi_taken      <= 1'b1;
      end
     else
      begin
      nmi_taken      <= nmi_taken;
      end
end
 
always @ (posedge clk )
begin
     if (reset)             core_reset     <= 1'b1;
     else
     if (!enable)           core_reset     <= core_reset;
     else                   core_reset     <= 1'b0;
 
end
 
always @ (posedge clk )
begin
     if (reset)             vector     <= 8'h00;
     else
     if (!enable)           vector     <= vector;
     else
     if(state == `RESET)    vector     <= BOOT_VEC;
     else                   vector     <= vec_int;
 
end
 
always @ (posedge clk )
begin
     if ( reset)            cmd            <= `cmd_none;
     else
     if (!enable)           cmd            <=  cmd;
     else
     if(state == `RESET)    cmd            <= `cmd_load_vec;
     else
     if(state == `HALT)     cmd            <= `cmd_load_vec;
     else
     if(nmi &&(!nmi_taken)) cmd            <= `cmd_load_vec;
     else                   cmd            <= `cmd_run;
end
 
endmodule

Line No.	Rev	Author	Line
1	131	jt_eaton
2			module `VARIANT`CONTROL
3
4			`#( parameter BOOT_VEC =8'hfc,`
5			`parameter STATE_SIZE=3`
6			`)`
7			`(`
8			`input wire clk,`
9			`input wire reset,`
10			`input wire enable,`
11			`input wire nmi,`
12			`input wire [7:0] vec_int,`
13			`input wire invalid,`
14			`input wire run_status,`
15			`input wire irq_status,`
16			`input wire brk_status,`
17			`input wire [STATE_SIZE:0] state,`
18			`input wire [2:0] ctrl,`
19			`input wire [7:0] ir,`
20			`input wire [15:0] address,`
21			`input wire branch_inst,`
22
23			`output reg [7:0] vector,`
24			`output reg [1:0] cmd,`
25			`output reg core_reset`
26			`);`
27
28
29			`reg nmi_taken ;`
30
31			`always @ (posedge clk )`
32			`begin`
33			`if (reset)`
34			`begin`
35			`nmi_taken <= 1'b0;`
36			`end`
37			`else`
38			`if (!nmi)`
39			`begin`
40			`nmi_taken <= 1'b0;`
41			`end`
42			`else`
43			if (ir == `RTI_IMP)
44			`begin`
45			`nmi_taken <= 1'b0;`
46			`end`
47			`else`
48			if (nmi && (state == `INT_1))
49			`begin`
50			`nmi_taken <= 1'b1;`
51			`end`
52			`else`
53			`begin`
54			`nmi_taken <= nmi_taken;`
55			`end`
56			`end`
57
58			`always @ (posedge clk )`
59			`begin`
60			`if (reset) core_reset <= 1'b1;`
61			`else`
62			`if (!enable) core_reset <= core_reset;`
63			`else core_reset <= 1'b0;`
64
65			`end`
66
67			`always @ (posedge clk )`
68			`begin`
69			`if (reset) vector <= 8'h00;`
70			`else`
71			`if (!enable) vector <= vector;`
72			`else`
73			if(state == `RESET) vector <= BOOT_VEC;
74			`else vector <= vec_int;`
75
76			`end`
77
78			`always @ (posedge clk )`
79			`begin`
80			if ( reset) cmd <= `cmd_none;
81			`else`
82			`if (!enable) cmd <= cmd;`
83			`else`
84			if(state == `RESET) cmd <= `cmd_load_vec;
85			`else`
86			if(state == `HALT) cmd <= `cmd_load_vec;
87			`else`
88			if(nmi &&(!nmi_taken)) cmd <= `cmd_load_vec;
89			else cmd <= `cmd_run;
90			`end`
91
92			`endmodule`

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [core/] [rtl/] [verilog/] [control] - Blame information for rev 131