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module `VARIANT`STATE_FSM
#(parameter STATE_SIZE=3)
(
    input  wire                 clk,
    input  wire                 reset,
    input  wire                 enable,
    input  wire                 run,
 
    input  wire [1:0]           cmd,
    input  wire [1:0]           length,
    input  wire                 now_fetch_op,
    input  wire                 absolute,
    input  wire                 immediate,
    input  wire                 implied,
    input  wire                 indirectx,
    input  wire                 indirecty,
    input  wire                 stack,
    input  wire                 relative,
    input  wire                 brk,
    input  wire                 rts,
    input  wire                 jump_indirect,
    input  wire                 jump,
    input  wire                 jsr,
    input  wire                 rti,
    input  wire                 branch_inst,
    input  wire [1:0]           ins_type,
    input  wire                 invalid,
 
    output reg  [STATE_SIZE:0] state
 
);
 
 
 
reg [STATE_SIZE:0]   next_state;
 
    always @ (posedge clk )
        begin
        if (reset)
              begin
              state            <=  `RESET;
              end
        else if(!enable)
              begin
              state            <= state ;
              end
 
        else  state            <= next_state;
        end
 
 
 
 
 
    always @ (*)
        begin
        next_state   = `RESET;
 
       if (reset)
            begin
            next_state = `RESET;
            end
       else
       if (invalid )
            begin
            next_state = `HALT;
            end
        else
 
       if ((cmd == `cmd_load_vec) &&  now_fetch_op      )
            begin
            if(state != `INT_1)            next_state = `INT_1;
            else                           next_state = `INT_2;
            end
        else
 
        case (state)
 
            `RESET:
                   begin
                   next_state = `INT_1;
                   end
 
            `HALT:
                   begin
                   next_state = `HALT;
                   end
 
            `FETCH_OP:
                   begin
                   next_state = `EXECUTE;
                   end
 
 
            `EXECUTE:
              begin
                  if(rts || rti)
                    next_state = `FETCH_OP;
                  else
                  if(indirectx)
                    next_state = `IDX_1;
                  else
                  if(indirecty)
                    next_state = `IDY_1;
                  else
                  if (absolute || jump || jsr || jump_indirect)
                    next_state = `AXE_1;
                  else
 
                  if(length == 2'b01)
                     begin
                     next_state = `EXECUTE;
                     end
                  else
                     begin
                     next_state = `EXE_1;
                     end
 
                end
 
            `EXE_1:
              begin
                  if(length == 2'b10)
                    begin
                    next_state = `EXECUTE;
                    end
                  else next_state = `AXE_2;
                end
 
            `AXE_1:
              begin
                 next_state = `AXE_2;
                end
 
 
 
 
            `AXE_2:
              begin
                  if(length == 2'b11)
                    begin
                    next_state = `EXECUTE;
                    end
                  else next_state = `HALT;
                end
 
            `IDX_1:
                    begin
                    next_state = `IDX_2;
                    end
 
            `IDX_2:
                    begin
                    next_state = `IDX_3;
                    end
 
            `IDX_3:
                    begin
                    next_state = `EXECUTE;
                    end
 
            `IDY_1:
                    begin
                    next_state = `IDY_2;
                    end
 
            `IDY_2:
                    begin
                    next_state = `IDY_3;
                    end
 
            `IDY_3:
                    begin
                    next_state = `EXECUTE;
                    end
 
            `INT_1:
                  begin
                  next_state = `INT_2;
                  end
 
            `INT_2:
                  begin
                  next_state = `FETCH_OP;
                  end
 
 
 
 
 
            default:
                begin
                next_state = `HALT;
                end
        endcase
    end
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
endmodule
 
 
 

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [core/] [rtl/] [verilog/] [state_fsm] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2			module `VARIANT`STATE_FSM
3			`#(parameter STATE_SIZE=3)`
4			`(`
5			`input wire clk,`
6			`input wire reset,`
7			`input wire enable,`
8			`input wire run,`
9
10			`input wire [1:0] cmd,`
11			`input wire [1:0] length,`
12			`input wire now_fetch_op,`
13			`input wire absolute,`
14			`input wire immediate,`
15			`input wire implied,`
16			`input wire indirectx,`
17			`input wire indirecty,`
18			`input wire stack,`
19			`input wire relative,`
20			`input wire brk,`
21			`input wire rts,`
22			`input wire jump_indirect,`
23			`input wire jump,`
24			`input wire jsr,`
25			`input wire rti,`
26			`input wire branch_inst,`
27			`input wire [1:0] ins_type,`
28			`input wire invalid,`
29
30			`output reg [STATE_SIZE:0] state`
31
32			`);`
33
34
35
36			`reg [STATE_SIZE:0] next_state;`
37
38			`always @ (posedge clk )`
39			`begin`
40			`if (reset)`
41			`begin`
42			state <= `RESET;
43			`end`
44			`else if(!enable)`
45			`begin`
46			`state <= state ;`
47			`end`
48
49			`else state <= next_state;`
50			`end`
51
52
53
54
55
56			`always @ (*)`
57			`begin`
58			next_state = `RESET;
59
60			`if (reset)`
61			`begin`
62			next_state = `RESET;
63			`end`
64			`else`
65			`if (invalid )`
66			`begin`
67			next_state = `HALT;
68			`end`
69			`else`
70
71			if ((cmd == `cmd_load_vec) && now_fetch_op )
72			`begin`
73			if(state != `INT_1) next_state = `INT_1;
74			else next_state = `INT_2;
75			`end`
76			`else`
77
78			`case (state)`
79
80			`RESET:
81			`begin`
82			next_state = `INT_1;
83			`end`
84
85			`HALT:
86			`begin`
87			next_state = `HALT;
88			`end`
89
90			`FETCH_OP:
91			`begin`
92			next_state = `EXECUTE;
93			`end`
94
95
96			`EXECUTE:
97			`begin`
98			`if(rts \|\| rti)`
99			next_state = `FETCH_OP;
100			`else`
101			`if(indirectx)`
102			next_state = `IDX_1;
103			`else`
104			`if(indirecty)`
105			next_state = `IDY_1;
106			`else`
107			`if (absolute \|\| jump \|\| jsr \|\| jump_indirect)`
108			next_state = `AXE_1;
109			`else`
110
111			`if(length == 2'b01)`
112			`begin`
113			next_state = `EXECUTE;
114			`end`
115			`else`
116			`begin`
117			next_state = `EXE_1;
118			`end`
119
120			`end`
121
122			`EXE_1:
123			`begin`
124			`if(length == 2'b10)`
125			`begin`
126			next_state = `EXECUTE;
127			`end`
128			else next_state = `AXE_2;
129			`end`
130
131			`AXE_1:
132			`begin`
133			next_state = `AXE_2;
134			`end`
135
136
137
138
139			`AXE_2:
140			`begin`
141			`if(length == 2'b11)`
142			`begin`
143			next_state = `EXECUTE;
144			`end`
145			else next_state = `HALT;
146			`end`
147
148			`IDX_1:
149			`begin`
150			next_state = `IDX_2;
151			`end`
152
153			`IDX_2:
154			`begin`
155			next_state = `IDX_3;
156			`end`
157
158			`IDX_3:
159			`begin`
160			next_state = `EXECUTE;
161			`end`
162
163			`IDY_1:
164			`begin`
165			next_state = `IDY_2;
166			`end`
167
168			`IDY_2:
169			`begin`
170			next_state = `IDY_3;
171			`end`
172
173			`IDY_3:
174			`begin`
175			next_state = `EXECUTE;
176			`end`
177
178			`INT_1:
179			`begin`
180			next_state = `INT_2;
181			`end`
182
183			`INT_2:
184			`begin`
185			next_state = `FETCH_OP;
186			`end`
187
188
189
190
191
192			`default:`
193			`begin`
194			next_state = `HALT;
195			`end`
196			`endcase`
197			`end`
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219			`endmodule`
220
221
222