URL https://opencores.org/ocsvn/socgen/socgen/trunk

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [core/] [rtl/] [verilog/] [top.rtl] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
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5			`//=============================================================================`
6			`// Rtl Glue Logic`
7			`//=============================================================================`
8
9			`assign cpu_pg0_data = pg0_add[0]?pg0_data[15:8]:pg0_data[7:0];`
10			`assign prog_rom_wr = we_pin && CSP;`
11			`assign prog_rom_wdata = {write_data,write_data};`
12			`assign core_ram_l_cs = CSD && (!addr_in[0]);`
13			`assign core_ram_h_cs = CSD && ( addr_in[0]);`
14			`assign pg00_ram_rd = pg0_rd\|\|(CS0 && rd_pin);`
15			`assign pg00_ram_l_wr = (pg0_wr\|\|(CS0 && we_pin)) && (!pg0_add[0]);`
16			`assign pg00_ram_h_wr = (pg0_wr\|\|(CS0 && we_pin)) && ( pg0_add[0]);`
17			`assign io_module_pic_irq_in = {ext_irq_in[2:0],ps2_data_avail,tx_irq,rx_irq,timer_irq};`
18			`assign io_module_vic_irq_in = {ext_irq_in[2:0],ps2_data_avail,tx_irq,rx_irq,timer_irq};`
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20			`//=============================================================================`
21			`//`
22			`//=============================================================================`
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