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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [core/] [rtl/] [xml/] [core_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Mos6502
core
def  default
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
 
 
 cpu
  
  
  
    
      
        addr
        addr
        150
        
      
      
        rdata
        rdata
        150
        
      
      
        wdata
        wdata
        70
        
      
      
        rd
        rd
        
      
      
        wr
        wr
        
      
    
 
 
 
 

 

 
 
 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
  
    
      destination
      top.out.sim
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
  
    
      destination
      top.out.syn
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

 
 
 
 
 
  
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/sim/top.out.sim
        verilogSourcemodule
      
 
 
 
      
        
        ../verilog/defines
        verilogSourceinclude
      
 
 
      
        alu
        ../verilog/alu
        verilogSourcemodule
      
 
      
        alu_logic
        ../verilog/alu_logic
        verilogSourcemodule
      
 
 
      
        control
        ../verilog/control
        verilogSourcemodule
      
 
 
      
        inst_decode
        ../verilog/inst_decode
        verilogSourcemodule
      
 
      
        sequencer
        ../verilog/sequencer
        verilogSourcemodule
      
 
 
 
      
        state_fsm
        ../verilog/state_fsm
        verilogSourcemodule
      
 
 
      
        
        ../verilog/top.sim
        verilogSourcefragment
      
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
 
 
    
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/syn/top.out.syn
        verilogSourcemodule
      
 
      
        
        ../verilog/defines
        verilogSourceinclude
      
 
 
      
        alu
        ../verilog/alu
        verilogSourcemodule
      
 
      
        alu_logic
        ../verilog/alu_logic
        verilogSourcemodule
      
 
 
      
        control
        ../verilog/control
        verilogSourcemodule
      
 
 
      
        inst_decode
        ../verilog/inst_decode
        verilogSourcemodule
      
 
      
        sequencer
        ../verilog/sequencer
        verilogSourcemodule
      
 
 
 
      
        state_fsm
        ../verilog/state_fsm
        verilogSourcemodule
      
 
 
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
 
 
 
 
  
 
 
 
 

       
 
       
       Hierarchical
       
                            spirit:library="Mos6502"
                            spirit:name="core"
                            spirit:version="def.design"/>
       
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
       
       sim:*Simulation:*
       Verilog
       fs-sim
       
 
       
       syn:*Synthesis:*
       Verilog
       fs-syn
       
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
      
 
 
 

 VEC_TABLE8'hff
 BOOT_VEC8'hfc

 
 
 

 
 
 
enable
wire
in

 
 
 
nmi
wire
in

 
vec_int
wire
in
70

 
 
prog_data
wire
in
150

 
 
pg0_data
wire
in
70

 
alu_status
wire
out
70

 
prog_counter
wire
out
150

 
pg0_add
wire
out
70

 
pg0_rd
wire
out

 
pg0_wr
wire
out

 
 
stk_push
wire
out

 
stk_push_data
wire
out
150

 
stk_pull
wire
out

 
stk_pull_data
wire
in
150

 
 
 

 

 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [core/] [rtl/] [xml/] [core_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Mos6502`
39			`core`
40			`def default`
41
42
43
44			`slave_clk`
45
46
47
48
49
50			`clk`
51			`clk`
52
53
54
55
56
57			`slave_reset`
58
59
60
61
62
63			`reset`
64			`reset`
65
66
67
68
69
70
71
72
73			`cpu`
74
75
76
77
78
79			`addr`
80			`addr`
81			`150`
82
83
84
85			`rdata`
86			`rdata`
87			`150`
88
89
90
91			`wdata`
92			`wdata`
93			`70`
94
95
96
97			`rd`
98			`rd`
99
100
101
102			`wr`
103			`wr`
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121			`gen_verilog_sim`
122			`104.0`
123			`none`
124			`:Simulation:`
125			`./tools/verilog/gen_verilog`
126
127
128			`destination`
129			`top.out.sim`
130
131
132			`dest_dir`
133			`../verilog`
134
135
136
137
138
139			`gen_verilog_syn`
140			`104.0`
141			`none`
142			`:Synthesis:`
143			`./tools/verilog/gen_verilog`
144
145
146			`destination`
147			`top.out.syn`
148
149
150			`dest_dir`
151			`../verilog`
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169			`fs-sim`
170
171
172
173			`../verilog/copyright.v`
174			`verilogSourceinclude`
175
176
177
178
179			`../verilog/sim/top.out.sim`
180			`verilogSourcemodule`
181
182
183
184
185
186
187			`../verilog/defines`
188			`verilogSourceinclude`
189
190
191
192
193			`alu`
194			`../verilog/alu`
195			`verilogSourcemodule`
196
197
198
199			`alu_logic`
200			`../verilog/alu_logic`
201			`verilogSourcemodule`
202
203
204
205
206			`control`
207			`../verilog/control`
208			`verilogSourcemodule`
209
210
211
212
213			`inst_decode`
214			`../verilog/inst_decode`
215			`verilogSourcemodule`
216
217
218
219			`sequencer`
220			`../verilog/sequencer`
221			`verilogSourcemodule`
222
223
224
225
226
227			`state_fsm`
228			`../verilog/state_fsm`
229			`verilogSourcemodule`
230
231
232
233
234
235			`../verilog/top.sim`
236			`verilogSourcefragment`
237
238
239
240
241			`../verilog/top.body`
242			`verilogSourcefragment`
243
244
245
246
247
248
249
250
251
252
253			`fs-syn`
254
255
256
257			`../verilog/copyright.v`
258			`verilogSourceinclude`
259
260
261
262
263
264			`../verilog/syn/top.out.syn`
265			`verilogSourcemodule`
266
267
268
269
270			`../verilog/defines`
271			`verilogSourceinclude`
272
273
274
275
276			`alu`
277			`../verilog/alu`
278			`verilogSourcemodule`
279
280
281
282			`alu_logic`
283			`../verilog/alu_logic`
284			`verilogSourcemodule`
285
286
287
288
289			`control`
290			`../verilog/control`
291			`verilogSourcemodule`
292
293
294
295
296			`inst_decode`
297			`../verilog/inst_decode`
298			`verilogSourcemodule`
299
300
301
302			`sequencer`
303			`../verilog/sequencer`
304			`verilogSourcemodule`
305
306
307
308
309
310			`state_fsm`
311			`../verilog/state_fsm`
312			`verilogSourcemodule`
313
314
315
316
317
318
319			`../verilog/top.body`
320			`verilogSourcefragment`
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339			`Hierarchical`
340
341			`spirit:library="Mos6502"`
342			`spirit:name="core"`
343			`spirit:version="def.design"/>`
344
345
346
347
348			`verilog`
349
350
351			`spirit:library="Testbench"`
352			`spirit:name="toolflow"`
353			`spirit:version="verilog"/>`
354
355
356
357
358
359
360
361
362			`sim:Simulation:`
363			`Verilog`
364			`fs-sim`
365
366
367
368			`syn:Synthesis:`
369			`Verilog`
370			`fs-syn`
371
372
373
374
375			`doc`
376
377
378			`spirit:library="Testbench"`
379			`spirit:name="toolflow"`
380			`spirit:version="documentation"/>`
381
382			`:Documentation:`
383			`Verilog`
384
385
386
387
388
389
390
391
392
393
394			`VEC_TABLE8'hff`
395			`BOOT_VEC8'hfc`
396
397
398
399
400
401
402
403
404			`enable`
405			`wire`
406			`in`
407
408
409
410
411			`nmi`
412			`wire`
413			`in`
414
415
416			`vec_int`
417			`wire`
418			`in`
419			`70`
420
421
422
423			`prog_data`
424			`wire`
425			`in`
426			`150`
427
428
429
430			`pg0_data`
431			`wire`
432			`in`
433			`70`
434
435
436			`alu_status`
437			`wire`
438			`out`
439			`70`
440
441
442			`prog_counter`
443			`wire`
444			`out`
445			`150`
446
447
448			`pg0_add`
449			`wire`
450			`out`
451			`70`
452
453
454			`pg0_rd`
455			`wire`
456			`out`
457
458
459			`pg0_wr`
460			`wire`
461			`out`
462
463
464
465			`stk_push`
466			`wire`
467			`out`
468
469
470			`stk_push_data`
471			`wire`
472			`out`
473			`150`
474
475
476			`stk_pull`
477			`wire`
478			`out`
479
480
481			`stk_pull_data`
482			`wire`
483			`in`
484			`150`
485
486
487
488
489
490
491
492
493
494
495
496
497
498