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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [cpu/] [rtl/] [xml/] [cpu_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
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http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
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opencores.org
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Mos6502
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cpu
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def  default
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 slave_clk
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        clk
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        clk
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 slave_reset
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        reset
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        reset
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 cpu
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        addr
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        addr
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        rdata
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        rdata
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        wdata
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        wdata
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        rd
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        rd
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        wr
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        wr
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    cpu
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    0x10000
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    8
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  gen_verilog_sim
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  104.0
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  none
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  :*Simulation:*
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  ./tools/verilog/gen_verilog
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      destination
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      top.out.sim
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      dest_dir
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      ../verilog
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      fs-sim
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        ../verilog/sim/top.out.sim
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        verilogSourcemodule
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        ../verilog/
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        verilogSourcelibraryDir
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      fs-syn
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        ../verilog/sim/top.out.sim
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        verilogSourcemodule
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        ../verilog/
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        verilogSourcelibraryDir
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              Hierarchical
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                                   spirit:library="Mos6502"
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                                   spirit:name="cpu"
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                                   spirit:version="def.design"/>
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              verilog
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                                   spirit:library="Testbench"
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                                   spirit:name="toolflow"
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                                   spirit:version="verilog"/>
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       sim:*Simulation:*
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       Verilog
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       fs-sim
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       syn:*Synthesis:*
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       Verilog
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       fs-syn
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              doc
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                                   spirit:library="Testbench"
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                                   spirit:name="toolflow"
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                                   spirit:version="documentation"/>
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              :*Documentation:*
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              Verilog
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 VEC_TABLE8'hff
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 BOOT_VEC8'hfc
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 CPU_ADD16
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 PROG_ROM_ADD0
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 PROG_ROM_WORDS0
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 PROG_ROM_FILE"NONE"
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enable
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wire
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in
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nmi
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wire
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in
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vec_int
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wire
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in
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pg0_data
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wire
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in
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alu_status
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wire
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out
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pg0_add
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wire
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out
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pg0_rd
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wire
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out
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pg0_wr
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wire
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out
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