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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [cpu/] [rtl/] [xml/] [cpu_def.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Mos6502
cpu
def  default
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
 
 
 cpu
  
  
 
           
 
    
      
        addr
        addr
        150
        
      
      
        rdata
        rdata
        150
        
      
      
        wdata
        wdata
        70
        
      
      
        rd
        rd
        
      
      
        wr
        wr
        
      
    
 
 

 
 

  
    cpu
    0x10000
    8
  

 
 
 
 
 

 
 
 
 
 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      configuration
      default
    
    
      dest_dir
      io_ports
    
  
 

 
 
 
 
 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
  
    
      destination
      top.out.sim
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 
 
 

 
 
 
 
 
  
 
 
    
      fs-sim
 
      
        
        ../verilog/sim/top.out.sim
        verilogSourcemodule
      
 
 
      
        
        ../verilog/
        verilogSourcelibraryDir
      
 
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/sim/top.out.sim
        verilogSourcemodule
      
 
 
      
        
        ../verilog/
        verilogSourcelibraryDir
      
 
 
 
    
 
 
 
 
 
 
  
 
 
 
 

       
 
 
              
              Hierarchical
 
              
                                   spirit:library="Mos6502"
                                   spirit:name="cpu"
                                   spirit:version="def.design"/>
              
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
       
       sim:*Simulation:*
       Verilog
       
       fs-sim
       
 
 
       
       syn:*Synthesis:*
       Verilog
       
       fs-syn
       
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
 
 

 VEC_TABLE8'hff
 BOOT_VEC8'hfc
 CPU_ADD16
 PROG_ROM_ADD0
 PROG_ROM_WORDS0
 PROG_ROM_WIDTH16
 PROG_ROM_DEFAULT16'hffff
 
 
 STACK_RAM_SIZE8
 STACK_RAM_WORDS256
 STACK_RAM_WIDTH16
 
 

 
 
 

 
 
 
enable
wire
in

 
 
 
nmi
wire
in

 
vec_int
wire
in
70

 
 
 
 
pg0_data
wire
in
70

 
alu_status
wire
out
70

 
 
pg0_add
wire
out
70

 
pg0_rd
wire
out

 
pg0_wr
wire
out

 
 
 

 

 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [cpu/] [rtl/] [xml/] [cpu_def.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Mos6502`
39			`cpu`
40			`def default`
41
42
43
44			`slave_clk`
45
46
47
48
49
50			`clk`
51			`clk`
52
53
54
55
56
57			`slave_reset`
58
59
60
61
62
63			`reset`
64			`reset`
65
66
67
68
69
70
71
72
73			`cpu`
74
75
76
77
78
79
80
81			`addr`
82			`addr`
83			`150`
84
85
86
87			`rdata`
88			`rdata`
89			`150`
90
91
92
93			`wdata`
94			`wdata`
95			`70`
96
97
98
99			`rd`
100			`rd`
101
102
103
104			`wr`
105			`wr`
106
107
108
109
110
111
112
113
114
115
116			`cpu`
117			`0x10000`
118			`8`
119
120
121
122
123
124
125
126
127
128	133	jt_eaton
129
130
131
132
133	131	jt_eaton
134	133	jt_eaton	`elab_verilog`
135			`102.1`
136			`none`
137			`:Simulation:`
138			`./tools/verilog/elab_verilog`
139
140
141			`configuration`
142			`default`
143
144
145			`dest_dir`
146			`io_ports`
147
148
149
150
151
152
153
154
155
156
157
158
159
160	131	jt_eaton	`gen_verilog_sim`
161			`104.0`
162			`none`
163			`:Simulation:`
164			`./tools/verilog/gen_verilog`
165
166
167			`destination`
168			`top.out.sim`
169
170
171			`dest_dir`
172			`../verilog`
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192			`fs-sim`
193
194
195
196			`../verilog/sim/top.out.sim`
197			`verilogSourcemodule`
198
199
200
201
202
203			`../verilog/`
204			`verilogSourcelibraryDir`
205
206
207
208
209
210
211
212
213
214			`fs-syn`
215
216
217
218			`../verilog/sim/top.out.sim`
219			`verilogSourcemodule`
220
221
222
223
224
225			`../verilog/`
226			`verilogSourcelibraryDir`
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248			`Hierarchical`
249
250
251			`spirit:library="Mos6502"`
252			`spirit:name="cpu"`
253			`spirit:version="def.design"/>`
254
255
256
257			`verilog`
258
259
260			`spirit:library="Testbench"`
261			`spirit:name="toolflow"`
262			`spirit:version="verilog"/>`
263
264
265
266
267
268
269
270
271
272			`sim:Simulation:`
273			`Verilog`
274
275			`fs-sim`
276
277
278
279
280			`syn:Synthesis:`
281			`Verilog`
282
283			`fs-syn`
284
285
286
287
288
289			`doc`
290
291
292			`spirit:library="Testbench"`
293			`spirit:name="toolflow"`
294			`spirit:version="documentation"/>`
295
296			`:Documentation:`
297			`Verilog`
298
299
300
301
302
303
304
305
306			`VEC_TABLE8'hff`
307			`BOOT_VEC8'hfc`
308			`CPU_ADD16`
309			`PROG_ROM_ADD0`
310			`PROG_ROM_WORDS0`
311	133	jt_eaton	`PROG_ROM_WIDTH16`
312			`PROG_ROM_DEFAULT16'hffff`
313
314
315			`STACK_RAM_SIZE8`
316			`STACK_RAM_WORDS256`
317			`STACK_RAM_WIDTH16`
318
319
320	131	jt_eaton
321
322
323
324
325
326
327
328			`enable`
329			`wire`
330			`in`
331
332
333
334
335			`nmi`
336			`wire`
337			`in`
338
339
340			`vec_int`
341			`wire`
342			`in`
343			`70`
344
345
346
347
348
349			`pg0_data`
350			`wire`
351			`in`
352			`70`
353
354
355			`alu_status`
356			`wire`
357			`out`
358			`70`
359
360
361
362			`pg0_add`
363			`wire`
364			`out`
365			`70`
366
367
368			`pg0_rd`
369			`wire`
370			`out`
371
372
373			`pg0_wr`
374			`wire`
375			`out`
376
377
378
379
380
381
382
383
384
385
386
387
388
389