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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [cpu/] [rtl/] [xml/] [cpu_def.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Mos6502
cpu
def  default
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
 
 
 cpu
  
  
 
           
 
    
      
        addr
        addr
        150
        
      
      
        rdata
        rdata
        150
        
      
      
        wdata
        wdata
        70
        
      
      
        rd
        rd
        
      
      
        wr
        wr
        
      
    
 
 

 
 

  
    cpu
    0x10000
    8
  

 
 
 
 
 

 
 
 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
  
    
      destination
      cpu_def
    
  

 
 
 
 
 
 

 
 
 
 
 
  
 
 
    
      fs-sim
 
      
        
        ../verilog/sim/cpu_def
        verilogSourcemodule
      
 
 
      
        
        ../verilog/
        verilogSourcelibraryDir
      
 
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/sim/cpu_def
        verilogSourcemodule
      
 
 
      
        
        ../verilog/
        verilogSourcelibraryDir
      
 
 
 
    
 
 
 
 
 
 
  
 
 
 
 

       
 
 
              
              Hierarchical
 
              
                                   spirit:library="Mos6502"
                                   spirit:name="cpu"
                                   spirit:version="def.design"/>
              
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
       
       sim:*Simulation:*
       Verilog
       
       fs-sim
       
 
 
       
       syn:*Synthesis:*
       Verilog
       
       fs-syn
       
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
 
 

 VEC_TABLE8'hff
 BOOT_VEC8'hfc
 CPU_ADD16
 PROG_ROM_ADD0
 PROG_ROM_WORDS0
 PROG_ROM_WIDTH16
 STACK_RAM_SIZE8
 STACK_RAM_WORDS256
 STACK_RAM_WIDTH16
 

 
 
 

 
 
 
enable
wire
in

 
 
 
nmi
wire
in

 
vec_int
wire
in
70

 
 
 
 
pg0_data
wire
in
70

 
alu_status
wire
out
70

 
 
pg0_add
wire
out
70

 
pg0_rd
wire
out

 
pg0_wr
wire
out

 
 
 

 

 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [cpu/] [rtl/] [xml/] [cpu_def.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Mos6502`
39			`cpu`
40			`def default`
41
42
43
44			`slave_clk`
45
46
47
48
49
50			`clk`
51			`clk`
52
53
54
55
56
57			`slave_reset`
58
59
60
61
62
63			`reset`
64			`reset`
65
66
67
68
69
70
71
72
73			`cpu`
74
75
76
77
78
79
80
81			`addr`
82			`addr`
83			`150`
84
85
86
87			`rdata`
88			`rdata`
89			`150`
90
91
92
93			`wdata`
94			`wdata`
95			`70`
96
97
98
99			`rd`
100			`rd`
101
102
103
104			`wr`
105			`wr`
106
107
108
109
110
111
112
113
114
115
116			`cpu`
117			`0x10000`
118			`8`
119
120
121
122
123
124
125
126
127
128	133	jt_eaton
129
130
131
132
133	131	jt_eaton
134			`gen_verilog_sim`
135			`104.0`
136			`none`
137			`:Simulation:`
138			`./tools/verilog/gen_verilog`
139
140
141			`destination`
142	134	jt_eaton	`cpu_def`
143	131	jt_eaton
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162			`fs-sim`
163
164
165
166	134	jt_eaton	`../verilog/sim/cpu_def`
167	131	jt_eaton	`verilogSourcemodule`
168
169
170
171
172
173			`../verilog/`
174			`verilogSourcelibraryDir`
175
176
177
178
179
180
181
182
183
184			`fs-syn`
185
186
187
188	134	jt_eaton	`../verilog/sim/cpu_def`
189	131	jt_eaton	`verilogSourcemodule`
190
191
192
193
194
195			`../verilog/`
196			`verilogSourcelibraryDir`
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218			`Hierarchical`
219
220
221			`spirit:library="Mos6502"`
222			`spirit:name="cpu"`
223			`spirit:version="def.design"/>`
224
225
226
227			`verilog`
228
229
230			`spirit:library="Testbench"`
231			`spirit:name="toolflow"`
232			`spirit:version="verilog"/>`
233
234
235
236
237
238
239
240
241
242			`sim:Simulation:`
243			`Verilog`
244
245			`fs-sim`
246
247
248
249
250			`syn:Synthesis:`
251			`Verilog`
252
253			`fs-syn`
254
255
256
257
258
259			`doc`
260
261
262			`spirit:library="Testbench"`
263			`spirit:name="toolflow"`
264			`spirit:version="documentation"/>`
265
266			`:Documentation:`
267			`Verilog`
268
269
270
271
272
273
274
275
276			`VEC_TABLE8'hff`
277			`BOOT_VEC8'hfc`
278			`CPU_ADD16`
279			`PROG_ROM_ADD0`
280			`PROG_ROM_WORDS0`
281	133	jt_eaton	`PROG_ROM_WIDTH16`
282			`STACK_RAM_SIZE8`
283			`STACK_RAM_WORDS256`
284			`STACK_RAM_WIDTH16`
285
286	131	jt_eaton
287
288
289
290
291
292
293
294			`enable`
295			`wire`
296			`in`
297
298
299
300
301			`nmi`
302			`wire`
303			`in`
304
305
306			`vec_int`
307			`wire`
308			`in`
309			`70`
310
311
312
313
314
315			`pg0_data`
316			`wire`
317			`in`
318			`70`
319
320
321			`alu_status`
322			`wire`
323			`out`
324			`70`
325
326
327
328			`pg0_add`
329			`wire`
330			`out`
331			`70`
332
333
334			`pg0_rd`
335			`wire`
336			`out`
337
338
339			`pg0_wr`
340			`wire`
341			`out`
342
343
344
345
346
347
348
349
350
351
352
353
354
355