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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [cpu/] [sim/] [testbenches/] [verilog/] [top.irq] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
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5			`//=============================================================================`
6			`// Irq assignments`
7			`//=============================================================================`
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9			`assign io_module_pic_irq_in = {3'b000,ps2_data_avail,tx_irq,rx_irq,timer_irq};`
10			`assign io_module_vic_irq_in = {3'b000,ps2_data_avail,tx_irq,rx_irq,timer_irq};`
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