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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [cpu/] [sim/] [testbenches/] [xml/] [cpu_def_tb.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Mos6502
cpu
def_tb
 

 

  elab_verilog
  103.0
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog

 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      tb.tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 

 
 


    VEC_TABLE8'hff
    BOOT_VEC8'hfc
    CPU_ADD16
    UART_MODEL_CLKCNT4'b1100
    UART_MODEL_SIZE4
    STARTUP"NONE"
    FONT"NONE"
    RAM_ADD11
    RAM_WORDS2048
    ROM_ADD12
    ROM_WORDS4096
    ROM_FILE"NONE"
    PROG_ROM_ADDROM_ADD
    PROG_ROM_WORDSROM_WORDS
    PROG_ROM_FILEROM_FILE

 
 
       
 
              
              Dut
              
              
                                   spirit:library="Mos6502"
                                   spirit:name="cpu"
                                   spirit:version="def_dut.params"/>
              
              
 
 
 
              
              Bfm
              
                                   spirit:library="Mos6502"
                                   spirit:name="cpu"
                                   spirit:version="bfm.design"/>
              
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 

 
 
 
 
 
 
 
 
 
  
 
 
    
      fs-common
 
 
      
        
        ../verilog/sram.load
        verilogSourcefragment
      
 
 
      
        
        ../verilog/top.rtl
        verilogSourcefragment
      
 
 
      
        
        ../verilog/top.irq
        verilogSourcefragment
      
 
 
    
 
 
 
    
      fs-sim
 
 
 
      
        
        ../verilog/common/tb.tb
        verilogSourcemodule
      
 
 
 
 
    
 
 
    
      fs-lint
 
 
 
      
        
        ../verilog/common/tb.tb
        verilogSourcemodule
      
 
 
    
 
 
 
  
 
 
 
 
 
 
 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [cpu/] [sim/] [testbenches/] [xml/] [cpu_def_tb.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Mos6502`
39			`cpu`
40			`def_tb`
41
42
43
44
45			`elab_verilog`
46			`103.0`
47			`none`
48			`:Simulation:`
49			`./tools/verilog/elab_verilog`
50
51
52
53			`gen_verilog`
54			`104.0`
55			`none`
56			`common`
57			`./tools/verilog/gen_verilog`
58
59
60			`destination`
61			`tb.tb`
62
63
64			`dest_dir`
65			`../verilog`
66
67
68			`top`
69
70
71
72
73
74
75
76
77
78
79			`VEC_TABLE8'hff`
80			`BOOT_VEC8'hfc`
81			`CPU_ADD16`
82			`UART_MODEL_CLKCNT4'b1100`
83			`UART_MODEL_SIZE4`
84			`STARTUP"NONE"`
85			`FONT"NONE"`
86			`RAM_ADD11`
87			`RAM_WORDS2048`
88			`ROM_ADD12`
89			`ROM_WORDS4096`
90			`ROM_FILE"NONE"`
91			`PROG_ROM_ADDROM_ADD`
92			`PROG_ROM_WORDSROM_WORDS`
93			`PROG_ROM_FILEROM_FILE`
94
95
96
97
98
99
100			`Dut`
101
102
103			`spirit:library="Mos6502"`
104			`spirit:name="cpu"`
105			`spirit:version="def_dut.params"/>`
106
107
108
109
110
111
112			`Bfm`
113
114			`spirit:library="Mos6502"`
115			`spirit:name="cpu"`
116			`spirit:version="bfm.design"/>`
117
118
119
120
121			`icarus`
122
123
124			`spirit:library="Testbench"`
125			`spirit:name="toolflow"`
126			`spirit:version="icarus"/>`
127
128
129
130
131
132			`commoncommon`
133			`Verilog`
134
135
136			`fs-common`
137
138
139
140
141
142			`sim:Simulation:`
143			`Verilog`
144
145
146			`fs-sim`
147
148
149
150
151
152			`lint:Lint:`
153			`Verilog`
154
155
156			`fs-lint`
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179			`fs-common`
180
181
182
183
184			`../verilog/sram.load`
185			`verilogSourcefragment`
186
187
188
189
190
191			`../verilog/top.rtl`
192			`verilogSourcefragment`
193
194
195
196
197
198			`../verilog/top.irq`
199			`verilogSourcefragment`
200
201
202
203
204
205
206
207
208			`fs-sim`
209
210
211
212
213
214			`../verilog/common/tb.tb`
215			`verilogSourcemodule`
216
217
218
219
220
221
222
223
224
225			`fs-lint`
226
227
228
229
230
231			`../verilog/common/tb.tb`
232			`verilogSourcemodule`
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251