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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [cpu/] [sim/] [testbenches/] [xml/] [cpu_def_tb.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Mos6502
cpu
def_tb
 

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      configuration
      default
    
    
      destination
      tb.tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 

 
 


    VEC_TABLE8'hff
    BOOT_VEC8'hfc
    CPU_ADD16
    UART_MODEL_CLKCNT4'b1100
    UART_MODEL_SIZE4
    STARTUP"NONE"
    FONT"NONE"
    RAM_ADD11
    RAM_WORDS2048
    ROM_ADD12
    ROM_WORDS4096
    ROM_FILE"NONE"
    PROG_ROM_ADDROM_ADD
    PROG_ROM_WORDSROM_WORDS
    PROG_ROM_FILEROM_FILE

 
 
       
 
              
              Dut
              
              
                                   spirit:library="Mos6502"
                                   spirit:name="cpu"
                                   spirit:version="def_dut.params"/>
              
              
 
 
 
              
              Bfm
              
                                   spirit:library="Mos6502"
                                   spirit:name="cpu"
                                   spirit:version="bfm.design"/>
              
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 

 
 
 
 
 
 
 
 
 
  
 
 
    
      fs-common
 
 
      
        
        ../verilog/sram.load
        verilogSourcefragment
      
 
 
      
        
        ../verilog/top.rtl
        verilogSourcefragment
      
 
 
      
        
        ../verilog/top.irq
        verilogSourcefragment
      
 
 
    
 
 
 
    
      fs-sim
 
 
 
      
        
        ../verilog/common/tb.tb
        verilogSourcemodule
      
 
 
 
 
    
 
 
    
      fs-lint
 
 
 
      
        
        ../verilog/common/tb.tb
        verilogSourcemodule
      
 
 
    
 
 
 
  
 
 
 
 
 
 
 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [cpu/] [sim/] [testbenches/] [xml/] [cpu_def_tb.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Mos6502`
39			`cpu`
40			`def_tb`
41
42
43
44
45	133	jt_eaton
46	131	jt_eaton
47			`gen_verilog`
48			`104.0`
49			`none`
50			`common`
51			`./tools/verilog/gen_verilog`
52
53
54	133	jt_eaton	`configuration`
55			`default`
56
57
58	131	jt_eaton	`destination`
59			`tb.tb`
60
61
62			`dest_dir`
63			`../verilog`
64
65
66			`top`
67
68
69
70
71
72
73
74
75
76
77			`VEC_TABLE8'hff`
78			`BOOT_VEC8'hfc`
79			`CPU_ADD16`
80			`UART_MODEL_CLKCNT4'b1100`
81			`UART_MODEL_SIZE4`
82			`STARTUP"NONE"`
83			`FONT"NONE"`
84			`RAM_ADD11`
85			`RAM_WORDS2048`
86			`ROM_ADD12`
87			`ROM_WORDS4096`
88			`ROM_FILE"NONE"`
89			`PROG_ROM_ADDROM_ADD`
90			`PROG_ROM_WORDSROM_WORDS`
91			`PROG_ROM_FILEROM_FILE`
92
93
94
95
96
97
98			`Dut`
99
100
101			`spirit:library="Mos6502"`
102			`spirit:name="cpu"`
103			`spirit:version="def_dut.params"/>`
104
105
106
107
108
109
110			`Bfm`
111
112			`spirit:library="Mos6502"`
113			`spirit:name="cpu"`
114			`spirit:version="bfm.design"/>`
115
116
117
118
119			`icarus`
120
121
122			`spirit:library="Testbench"`
123			`spirit:name="toolflow"`
124			`spirit:version="icarus"/>`
125
126
127
128
129
130			`commoncommon`
131			`Verilog`
132
133
134			`fs-common`
135
136
137
138
139
140			`sim:Simulation:`
141			`Verilog`
142
143
144			`fs-sim`
145
146
147
148
149
150			`lint:Lint:`
151			`Verilog`
152
153
154			`fs-lint`
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177			`fs-common`
178
179
180
181
182			`../verilog/sram.load`
183			`verilogSourcefragment`
184
185
186
187
188
189			`../verilog/top.rtl`
190			`verilogSourcefragment`
191
192
193
194
195
196			`../verilog/top.irq`
197			`verilogSourcefragment`
198
199
200
201
202
203
204
205
206			`fs-sim`
207
208
209
210
211
212			`../verilog/common/tb.tb`
213			`verilogSourcemodule`
214
215
216
217
218
219
220
221
222
223			`fs-lint`
224
225
226
227
228
229			`../verilog/common/tb.tb`
230			`verilogSourcemodule`
231
232
233
234
235
236
237
238
239
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242
243
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