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1 131 jt_eaton 
;
2 
; 6 5 0 2   F U N C T I O N A L   T E S T S
3 
;
4 
; Copyright (C) 2012  Klaus Dormann
5 
;
6 
; This program is free software: you can redistribute it and/or modify
7 
; it under the terms of the GNU General Public License as published by
8 
; the Free Software Foundation, either version 3 of the License, or
9 
; (at your option) any later version.
10 
;
11 
; This program is distributed in the hope that it will be useful,
12 
; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 
; GNU General Public License for more details.
15 
;
16 
; You should have received a copy of the GNU General Public License
17 
; along with this program.  If not, see .
18 
 
19 
 
20 
; This program is designed to test all opcodes of a 6502 emulator using all
21 
; addressing modes with focus on propper setting of the processor status
22 
; register bits.
23 
;
24 
; version 01-aug-2012
25 
; contact info at http://2m5.de or email K@2m5.de
26 
;
27 
; assembled with AS65 from http://www.kingswood-consulting.co.uk/assemblers/
28 
; command line switches: -l -m -s2 -w -h0
29 
;                         |  |  |   |  no page headers in listing
30 
;                         |  |  |   wide listing (133 char/col)
31 
;                         |  |  write intel hex file instead of binary
32 
;                         |  expand macros in listing
33 
;                         generate pass2 listing
34 
;
35 
; No IO - should be run from a monitor with access to registers.
36 
; To run load intel hex image with a load command, than alter PC to 1000 hex and
37 
; enter a go command.
38 
; Loop on program counter determines error or successful completion of test.
39 
; Check listing for relevant traps (jump/branch *).
40 
; Please note that in early tests some instructions will have to be used before
41 
; they are actually tested!
42 
;
43 
; RESET, NMI or IRQ should not occur and will be trapped if vectors are enabled.
44 
; Tests documented behavior of the original NMOS 6502 only! No unofficial
45 
; opcodes. Additional opcodes of newer versions of the CPU (65C02, 65816) will
46 
; not be tested. Decimal ops will only be tested with valid BCD operands and
47 
; N V Z flags will be ignored.
48 
;
49 
; Debugging hints:
50 
;     Most of the code is written sequentially. if you hit a trap, check the
51 
;   immediately preceeding code for the instruction to be tested. Results are
52 
;   tested first, flags are checked second by pushing them onto the stack and
53 
;   pulling them to the accumulator after the result was checked. The "real"
54 
;   flags are no longer valid for the tested instruction at this time!
55 
;     If the tested instruction was indexed, the relevant index (X or Y) must
56 
;   also be checked. Opposed to the flags, X and Y registers are still valid.
57 
;
58 
; versions:
59 
;   28-jul-2012  1st version distributed for testing
60 
;   29-jul-2012  fixed references to location 0, now #0
61 
;                added license - GPLv3
62 
;   30-jul-2012  added configuration options
63 
;   01-aug-2012  added trap macro to allow user to change error handling
64 
 
65 
 
66 
; C O N F I G U R A T I O N
67 
;
68 
;ROM_vectors writable (0=no, 1=yes)
69 
;if ROM vectors can not be used interrupts will not be trapped
70 
;as a consequence BRK can not be tested but will be emulated to test RTI
71 
ROM_vectors = 1
72 
;load_data_direct (0=move from code segment, 1=load directly)
73 
;loading directly is preferred but may not be supported by your platform
74 
;0 produces only consecutive object code, 1 is not suitable for a binary image
75 
load_data_direct = 1
76 
;I_flag behavior (0=force enabled, 1=force disabled, 2=prohibit change, 3=allow
77 
;change) 2 requires extra code and is not recommended. SEI & CLI can only be
78 
;tested if you allow changing the interrupt status (I_flag = 3)
79 
I_flag = 3
80 
;configure memory - try to stay away from memory used by the system
81 
;zero_page memory start address, $55 (85) consecutive Bytes required
82 
;                                add 2 if I_flag = 2
83 
zero_page = $0
84 
;data_segment memory start address, $5A (90) consecutive Bytes required Changed from $a
85 
data_segment = $200
86 
;code_segment memory start address, 12kB of consecutive space required
87 
;                                   add 2.5 kB if I_flag = 2
88 
;parts of the code are self modifying and must reside in RAM
89 
code_segment = $c000
90 
 
91 
;macros for error & success traps to allow user modification
92 
;example:
93 
;trap    macro
94 
;        jsr my_error_handler
95 
;        endm
96 
;trap_eq macro
97 
;        bne skip\?
98 
;        trap           ;failed equal (zero)
99 
;skip\?
100 
;        endm
101 
trap    macro
102 
        jmp *           ;failed anyway
103 
        endm
104 
trap_eq macro
105 
        beq *           ;failed equal (zero)
106 
        endm
107 
trap_ne macro
108 
        bne *           ;failed not equal (non zero)
109 
        endm
110 
trap_cs macro
111 
        bcs *           ;failed carry set
112 
        endm
113 
trap_cc macro
114 
        bcc *           ;failed carry clear
115 
        endm
116 
trap_mi macro
117 
        bmi *           ;failed minus (bit 7 set)
118 
        endm
119 
trap_pl macro
120 
        bpl *           ;failed plus (bit 7 clear)
121 
        endm
122 
trap_vs macro
123 
        bvs *           ;failed overflow set
124 
        endm
125 
trap_vc macro
126 
        bvc *           ;failed overflow clear
127 
        endm
128 
success macro
129 
        jmp *           ;test passed, no errors
130 
        endm
131 
 
132 
 
133 
carry   equ %00000001   ;flag bits in status
134 
zero    equ %00000010
135 
intdis  equ %00000100
136 
decmode equ %00001000
137 
break   equ %00010000
138 
reserv  equ %00100000
139 
overfl  equ %01000000
140 
minus   equ %10000000
141 
 
142 
fc      equ carry
143 
fz      equ zero
144 
fzc     equ carry+zero
145 
fv      equ overfl
146 
fvz     equ overfl+zero
147 
fn      equ minus
148 
fnc     equ minus+carry
149 
fnz     equ minus+zero
150 
fnzc    equ minus+zero+carry
151 
fnv     equ minus+overfl
152 
 
153 
fao     equ break+reserv    ;bits always on after PHP, BRK
154 
fai     equ fao+intdis      ;+ forced interrupt disable
155 
m8      equ $ff             ;8 bit mask
156 
m8i     equ $ff&~intdis     ;8 bit mask - interrupt disable
157 
 
158 
;macros to allow masking of status bits.
159 
;masking of interrupt enable/disable on load and compare
160 
;masking of always on bits after PHP or BRK (unused & break) on compare
161 
        if I_flag = 0
162 
load_flag   macro
163 
            lda #\1&m8i         ;force enable interrupts (mask I)
164 
            endm
165 
cmp_flag    macro
166 
            cmp #(\1|fao)&m8i   ;I_flag is always enabled + always on bits
167 
            endm
168 
eor_flag    macro
169 
            eor #(\1&m8i|fao)   ;mask I, invert expected flags + always on bits
170 
            endm
171 
        endif
172 
        if I_flag = 1
173 
load_flag   macro
174 
            lda #\1|intdis      ;force disable interrupts
175 
            endm
176 
cmp_flag    macro
177 
            cmp #(\1|fai)&m8    ;I_flag is always disabled + always on bits
178 
            endm
179 
eor_flag    macro
180 
            eor #(\1|fai)       ;invert expected flags + always on bits + I
181 
            endm
182 
        endif
183 
        if I_flag = 2
184 
load_flag   macro
185 
            lda #\1
186 
            ora flag_I_on       ;restore I-flag
187 
            and flag_I_off
188 
            endm
189 
cmp_flag    macro
190 
            eor flag_I_on       ;I_flag is never changed
191 
            cmp #(\1|fao)&m8i   ;expected flags + always on bits, mask I
192 
            endm
193 
eor_flag    macro
194 
            eor flag_I_on       ;I_flag is never changed
195 
            eor #(\1&m8i|fao)   ;mask I, invert expected flags + always on bits
196 
            endm
197 
        endif
198 
        if I_flag = 3
199 
load_flag   macro
200 
            lda #\1             ;allow test to change I-flag (no mask)
201 
            endm
202 
cmp_flag    macro
203 
            cmp #(\1|fao)&m8    ;expected flags + always on bits
204 
            endm
205 
eor_flag    macro
206 
            eor #\1|fao         ;invert expected flags + always on bits
207 
            endm
208 
        endif
209 
 
210 
;macros to set (register|memory|zeropage) & status
211 
set_stat    macro       ;setting flags in the processor status register
212 
            load_flag \1
213 
            pha         ;use stack to load status
214 
            plp
215 
            endm
216 
 
217 
set_a       macro       ;precharging accu & status
218 
            load_flag \2
219 
            pha         ;use stack to load status
220 
            lda #\1     ;precharge accu
221 
            plp
222 
            endm
223 
 
224 
set_x       macro       ;precharging index & status
225 
            load_flag \2
226 
            pha         ;use stack to load status
227 
            ldx #\1     ;precharge index x
228 
            plp
229 
            endm
230 
 
231 
set_y       macro       ;precharging index & status
232 
            load_flag \2
233 
            pha         ;use stack to load status
234 
            ldy #\1     ;precharge index y
235 
            plp
236 
            endm
237 
 
238 
set_ax      macro       ;precharging indexed accu & immediate status
239 
            load_flag \2
240 
            pha         ;use stack to load status
241 
            lda \1,x    ;precharge accu
242 
            plp
243 
            endm
244 
 
245 
set_ay      macro       ;precharging indexed accu & immediate status
246 
            load_flag \2
247 
            pha         ;use stack to load status
248 
            lda \1,y    ;precharge accu
249 
            plp
250 
            endm
251 
 
252 
set_z       macro       ;precharging indexed zp & immediate status
253 
            load_flag \2
254 
            pha         ;use stack to load status
255 
            lda \1,x    ;load to zeropage
256 
            sta zpt
257 
            plp
258 
            endm
259 
 
260 
set_zx      macro       ;precharging zp,x & immediate status
261 
            load_flag \2
262 
            pha         ;use stack to load status
263 
            lda \1,x    ;load to indexed zeropage
264 
            sta zpt,x
265 
            plp
266 
            endm
267 
 
268 
set_abs     macro       ;precharging indexed memory & immediate status
269 
            load_flag \2
270 
            pha         ;use stack to load status
271 
            lda \1,x    ;load to memory
272 
            sta abst
273 
            plp
274 
            endm
275 
 
276 
set_absx    macro       ;precharging abs,x & immediate status
277 
            load_flag \2
278 
            pha         ;use stack to load status
279 
            lda \1,x    ;load to indexed memory
280 
            sta abst,x
281 
            plp
282 
            endm
283 
 
284 
;macros to test (register|memory|zeropage) & status & (mask)
285 
tst_stat    macro       ;testing flags in the processor status register
286 
            php         ;save status
287 
            php         ;use stack to retrieve status
288 
            pla
289 
            cmp_flag \1
290 
            trap_ne
291 
            plp         ;restore status
292 
            endm
293 
 
294 
tst_a       macro       ;testing result in accu & flags
295 
            php         ;save flags
296 
            php
297 
            cmp #\1     ;test result
298 
            trap_ne
299 
            pla         ;load status
300 
            cmp_flag \2
301 
            trap_ne
302 
            plp         ;restore status
303 
            endm
304 
 
305 
tst_x       macro       ;testing result in x index & flags
306 
            php         ;save flags
307 
            php
308 
            cpx #\1     ;test result
309 
            trap_ne
310 
            pla         ;load status
311 
            cmp_flag \2
312 
            trap_ne
313 
            plp         ;restore status
314 
            endm
315 
 
316 
tst_y       macro       ;testing result in y index & flags
317 
            php         ;save flags
318 
            php
319 
            cpy #\1     ;test result
320 
            trap_ne
321 
            pla         ;load status
322 
            cmp_flag \2
323 
            trap_ne
324 
            plp         ;restore status
325 
            endm
326 
 
327 
tst_ax      macro       ;indexed testing result in accu & flags
328 
            php         ;save flags
329 
            cmp \1,x    ;test result
330 
            trap_ne
331 
            pla         ;load status
332 
            eor_flag \3
333 
            cmp \2,x    ;test flags
334 
            trap_ne     ;
335 
            endm
336 
 
337 
tst_ay      macro       ;indexed testing result in accu & flags
338 
            php         ;save flags
339 
            cmp \1,y    ;test result
340 
            trap_ne     ;
341 
            pla         ;load status
342 
            eor_flag \3
343 
            cmp \2,y    ;test flags
344 
            trap_ne
345 
            endm
346 
 
347 
tst_z       macro       ;indexed testing result in zp & flags
348 
            php         ;save flags
349 
            lda zpt
350 
            cmp \1,x    ;test result
351 
            trap_ne
352 
            pla         ;load status
353 
            eor_flag \3
354 
            cmp \2,x    ;test flags
355 
            trap_ne
356 
            endm
357 
 
358 
tst_zx      macro       ;testing result in zp,x & flags
359 
            php         ;save flags
360 
            lda zpt,x
361 
            cmp \1,x    ;test result
362 
            trap_ne
363 
            pla         ;load status
364 
            eor_flag \3
365 
            cmp \2,x    ;test flags
366 
            trap_ne
367 
            endm
368 
 
369 
tst_abs     macro       ;indexed testing result in memory & flags
370 
            php         ;save flags
371 
            lda abst
372 
            cmp \1,x    ;test result
373 
            trap_ne
374 
            pla         ;load status
375 
            eor_flag \3
376 
            cmp \2,x    ;test flags
377 
            trap_ne
378 
            endm
379 
 
380 
tst_absx    macro       ;testing result in abs,x & flags
381 
            php         ;save flags
382 
            lda abst,x
383 
            cmp \1,x    ;test result
384 
            trap_ne
385 
            pla         ;load status
386 
            eor_flag \3
387 
            cmp \2,x    ;test flags
388 
            trap_ne
389 
            endm
390 
 
391 
 
392 
    if load_data_direct = 1
393 
        data
394 
    else
395 
        bss                 ;uninitialized segment, copy of data at end of code!
396 
    endif
397 
        org zero_page
398 
zp_bss
399 
zp1     db  $c3,$82,$41,0   ;test patterns for LDx BIT ROL ROR ASL LSR
400 
zp7f    db  $7f             ;test pattern for compare
401 
zpt     ds  5               ;store/modify test area
402 
;logical zeropage operands
403 
zpOR    db  0,$1f,$71,$80   ;test pattern for OR
404 
zpAN    db  $0f,$ff,$7f,$80 ;test pattern for AND
405 
zpEO    db  $ff,$0f,$8f,$8f ;test pattern for EOR
406 
;indirect addressing pointers
407 
ind1    dw  abs1            ;indirect pointer to pattern in absolute memory
408 
        dw  abs1+1
409 
        dw  abs1+2
410 
        dw  abs1+3
411 
        dw  abs7f
412 
inw1    dw  abs1-$f8        ;indirect pointer for wrap-test pattern
413 
indt    dw  abst            ;indirect pointer to store area in absolute memory
414 
        dw  abst+1
415 
        dw  abst+2
416 
        dw  abst+3
417 
inwt    dw  abst-$f8        ;indirect pointer for wrap-test store
418 
indAN   dw  absAN           ;indirect pointer to AND pattern in absolute memory
419 
        dw  absAN+1
420 
        dw  absAN+2
421 
        dw  absAN+3
422 
indEO   dw  absEO           ;indirect pointer to EOR pattern in absolute memory
423 
        dw  absEO+1
424 
        dw  absEO+2
425 
        dw  absEO+3
426 
indOR   dw  absOR           ;indirect pointer to OR pattern in absolute memory
427 
        dw  absOR+1
428 
        dw  absOR+2
429 
        dw  absOR+3
430 
;add/subtract operand generation and result/flag prediction
431 
adi2    dw  ada2            ;indirect pointer to operand 2 in absolute memory
432 
sbi2    dw  sba2            ;indirect pointer to complemented operand 2 (SBC)
433 
adiy2   dw  ada2-$ff        ;with offset for indirect indexed
434 
sbiy2   dw  sba2-$ff
435 
zp_bss_end
436 
adfc    ds  1               ;carry flag before op
437 
ad1     ds  1               ;operand 1 - accumulator
438 
ad2     ds  1               ;operand 2 - memory / immediate
439 
adrl    ds  1               ;expected result bits 0-7
440 
adrh    ds  1               ;expected result bit 8 (carry)
441 
adrf    ds  1               ;expected flags NV0000ZC (not valid in decimal mode)
442 
sb2     ds  1               ;operand 2 complemented for subtract
443 
;break test interrupt save
444 
irq_a   ds  1               ;a register
445 
irq_x   ds  1               ;x register
446 
    if I_flag = 2
447 
;masking for I bit in status
448 
flag_I_on   ds  1           ;or mask to load flags
449 
flag_I_off  ds  1           ;and mask to load flags
450 
    endif
451 
 
452 
        org data_segment
453 
data_bss
454 
abs1    db  $c3,$82,$41,0   ;test patterns for LDx BIT ROL ROR ASL LSR
455 
abs7f   db  $7f             ;test pattern for compare
456 
;loads
457 
fLDx    db  fn,fn,0,fz      ;expected flags for load
458 
;shifts
459 
rASL                        ;expected result ASL & ROL -carry
460 
rROL    db  $86,$04,$82,0   ; "
461 
rROLc   db  $87,$05,$83,1   ;expected result ROL +carry
462 
rLSR                        ;expected result LSR & ROR -carry
463 
rROR    db  $61,$41,$20,0   ; "
464 
rRORc   db  $e1,$c1,$a0,$80 ;expected result ROR +carry
465 
fASL                        ;expected flags for shifts
466 
fROL    db  fnc,fc,fn,fz    ;no carry in
467 
fROLc   db  fnc,fc,fn,0     ;carry in
468 
fLSR
469 
fROR    db  fc,0,fc,fz      ;no carry in
470 
fRORc   db  fnc,fn,fnc,fn   ;carry in
471 
;increments (decrements)
472 
rINC    db  $7f,$80,$ff,0,1 ;expected result for INC/DEC
473 
fINC    db  0,fn,fn,fz,0    ;expected flags for INC/DEC
474 
abst    ds  5               ;store/modify test area
475 
;logical memory operand
476 
absOR   db  0,$1f,$71,$80   ;test pattern for OR
477 
absAN   db  $0f,$ff,$7f,$80 ;test pattern for AND
478 
absEO   db  $ff,$0f,$8f,$8f ;test pattern for EOR
479 
;logical accu operand
480 
absORa  db  0,$f1,$1f,0     ;test pattern for OR
481 
absANa  db  $f0,$ff,$ff,$ff ;test pattern for AND
482 
absEOa  db  $ff,$f0,$f0,$0f ;test pattern for EOR
483 
;logical results
484 
absrlo  db  0,$ff,$7f,$80
485 
absflo  db  fz,fn,0,fn
486 
data_bss_end
487 
;add/subtract operand copy
488 
ada2    ds  1               ;operand 2
489 
sba2    ds  1               ;operand 2 complemented for subtract
490 
 
491 
 
492 
        code
493 
        org code_segment
494 
start   cld
495 
 
496 
        lda #$00
497 
        sta $8002
498 
;stop interrupts before initializing BSS
499 
    if I_flag = 1
500 
        sei
501 
    endif
502 
 
503 
;initialize BSS segment
504 
    if load_data_direct != 1
505 
        ldx #zp_end-zp_init-1
506 
ld_zp   lda zp_init,x
507 
        sta zp_bss,x
508 
        dex
509 
        bpl ld_zp
510 
        ldx #data_end-data_init-1
511 
ld_data lda data_init,x
512 
        sta data_bss,x
513 
        dex
514 
        bpl ld_data
515 
    endif
516 
 
517 
;retain status of interrupt flag
518 
    if I_flag = 2
519 
        php
520 
        pla
521 
        and #4          ;isolate flag
522 
        sta flag_I_on   ;or mask
523 
        eor #lo(~4)     ;reverse
524 
        sta flag_I_off  ;and mask
525 
    endif
526 
 
527 
;testing relative addressing with BEQ
528 
        ldy #$fe        ;testing maximum range, not -1/-2 (invalid/self adr)
529 
range_loop
530 
        dey             ;next relative address
531 
        tya
532 
        tax             ;precharge count to end of loop
533 
        bpl range_fw    ;calculate relative address
534 
        clc             ;avoid branch self or to relative address of branch
535 
        adc #2
536 
range_fw
537 
        eor #$7f        ;complement except sign
538 
        sta range_adr   ;load into test target
539 
        lda #0          ;should set zero flag in status register
540 
        jmp range_op
541 
 
542 
        ;relative address target field with branch under test in the middle
543 
        dex             ;-128 - max backward
544 
        dex
545 
        dex
546 
        dex
547 
        dex
548 
        dex
549 
        dex
550 
        dex
551 
        dex             ;-120
552 
        dex
553 
        dex
554 
        dex
555 
        dex
556 
        dex
557 
        dex
558 
        dex
559 
        dex
560 
        dex
561 
        dex             ;-110
562 
        dex
563 
        dex
564 
        dex
565 
        dex
566 
        dex
567 
        dex
568 
        dex
569 
        dex
570 
        dex
571 
        dex             ;-100
572 
        dex
573 
        dex
574 
        dex
575 
        dex
576 
        dex
577 
        dex
578 
        dex
579 
        dex
580 
        dex
581 
        dex             ;-90
582 
        dex
583 
        dex
584 
        dex
585 
        dex
586 
        dex
587 
        dex
588 
        dex
589 
        dex
590 
        dex
591 
        dex             ;-80
592 
        dex
593 
        dex
594 
        dex
595 
        dex
596 
        dex
597 
        dex
598 
        dex
599 
        dex
600 
        dex
601 
        dex             ;-70
602 
        dex
603 
        dex
604 
        dex
605 
        dex
606 
        dex
607 
        dex
608 
        dex
609 
        dex
610 
        dex
611 
        dex             ;-60
612 
        dex
613 
        dex
614 
        dex
615 
        dex
616 
        dex
617 
        dex
618 
        dex
619 
        dex
620 
        dex
621 
        dex             ;-50
622 
        dex
623 
        dex
624 
        dex
625 
        dex
626 
        dex
627 
        dex
628 
        dex
629 
        dex
630 
        dex
631 
        dex             ;-40
632 
        dex
633 
        dex
634 
        dex
635 
        dex
636 
        dex
637 
        dex
638 
        dex
639 
        dex
640 
        dex
641 
        dex             ;-30
642 
        dex
643 
        dex
644 
        dex
645 
        dex
646 
        dex
647 
        dex
648 
        dex
649 
        dex
650 
        dex
651 
        dex             ;-20
652 
        dex
653 
        dex
654 
        dex
655 
        dex
656 
        dex
657 
        dex
658 
        dex
659 
        dex
660 
        dex
661 
        dex             ;-10
662 
        dex
663 
        dex
664 
        dex
665 
        dex
666 
        dex
667 
        dex
668 
        dex             ;-3
669 
range_op                ;test target with zero flag=0, z=1 if previous dex
670 
range_adr   = *+1       ;modifiable relative address
671 
        trap_eq         ;if called without modification
672 
        dex             ;+0
673 
        dex
674 
        dex
675 
        dex
676 
        dex
677 
        dex
678 
        dex
679 
        dex
680 
        dex
681 
        dex
682 
        dex             ;+10
683 
        dex
684 
        dex
685 
        dex
686 
        dex
687 
        dex
688 
        dex
689 
        dex
690 
        dex
691 
        dex
692 
        dex             ;+20
693 
        dex
694 
        dex
695 
        dex
696 
        dex
697 
        dex
698 
        dex
699 
        dex
700 
        dex
701 
        dex
702 
        dex             ;+30
703 
        dex
704 
        dex
705 
        dex
706 
        dex
707 
        dex
708 
        dex
709 
        dex
710 
        dex
711 
        dex
712 
        dex             ;+40
713 
        dex
714 
        dex
715 
        dex
716 
        dex
717 
        dex
718 
        dex
719 
        dex
720 
        dex
721 
        dex
722 
        dex             ;+50
723 
        dex
724 
        dex
725 
        dex
726 
        dex
727 
        dex
728 
        dex
729 
        dex
730 
        dex
731 
        dex
732 
        dex             ;+60
733 
        dex
734 
        dex
735 
        dex
736 
        dex
737 
        dex
738 
        dex
739 
        dex
740 
        dex
741 
        dex
742 
        dex             ;+70
743 
        dex
744 
        dex
745 
        dex
746 
        dex
747 
        dex
748 
        dex
749 
        dex
750 
        dex
751 
        dex
752 
        dex             ;+80
753 
        dex
754 
        dex
755 
        dex
756 
        dex
757 
        dex
758 
        dex
759 
        dex
760 
        dex
761 
        dex
762 
        dex             ;+90
763 
        dex
764 
        dex
765 
        dex
766 
        dex
767 
        dex
768 
        dex
769 
        dex
770 
        dex
771 
        dex
772 
        dex             ;+100
773 
        dex
774 
        dex
775 
        dex
776 
        dex
777 
        dex
778 
        dex
779 
        dex
780 
        dex
781 
        dex
782 
        dex             ;+110
783 
        dex
784 
        dex
785 
        dex
786 
        dex
787 
        dex
788 
        dex
789 
        dex
790 
        dex
791 
        dex
792 
        dex             ;+120
793 
        dex
794 
        dex
795 
        dex
796 
        dex
797 
        dex
798 
        dex
799 
        beq range_ok    ;+127 - max forward
800 
        trap            ; bad range
801 
range_ok
802 
        cpy #0
803 
        beq range_end
804 
        jmp range_loop
805 
range_end               ;range test successful
806 
 
807 
;partial test BNE & CMP, CPX, CPY immediate
808 
        cpy #1          ;testing BNE true
809 
        bne test_bne
810 
        trap
811 
test_bne
812 
        lda #0
813 
        cmp #0          ;test compare immediate
814 
        trap_ne
815 
        trap_cc
816 
        trap_mi
817 
        cmp #1
818 
        trap_eq
819 
        trap_cs
820 
        trap_pl
821 
        tax
822 
        cpx #0          ;test compare x immediate
823 
        trap_ne
824 
        trap_cc
825 
        trap_mi
826 
        cpx #1
827 
        trap_eq
828 
        trap_cs
829 
        trap_pl
830 
        tay
831 
        cpy #0          ;test compare y immediate
832 
        trap_ne
833 
        trap_cc
834 
        trap_mi
835 
        cpy #1
836 
        trap_eq
837 
        trap_cs
838 
        trap_pl
839 
;testing stack operations PHA PHP PLA PLP
840 
;testing branch decisions BPL BMI BVC BVS BCC BCS BNE BEQ
841 
 
842 
        ldx #$ff        ;initialize stack
843 
        txs
844 
        lda #$55
845 
        pha
846 
        lda #$aa
847 
        pha
848 
        cmp $1fe        ;on stack ?
849 
        trap_ne
850 
        tsx
851 
        txa             ;overwrite accu
852 
        cmp #$fd        ;sp decremented?
853 
        trap_ne
854 
        pla
855 
        cmp #$aa        ;successful retreived from stack?
856 
        trap_ne
857 
        pla
858 
        cmp #$55
859 
        trap_ne
860 
        cmp $1ff        ;remains on stack?
861 
        trap_ne
862 
        tsx
863 
        cpx #$ff        ;sp incremented?
864 
        trap_ne
865 
        set_stat $ff    ;all on
866 
        trap_pl         ;branches should not be taken
867 
        trap_vc
868 
        trap_cc
869 
        trap_ne
870 
        bmi br1         ;branches should be taken
871 
        trap
872 
br1     bvs br2
873 
        trap
874 
br2     bcs br3
875 
        trap
876 
br3     beq br4
877 
        trap
878 
br4     php
879 
        tsx
880 
        cpx #$fe        ;sp after php?
881 
        trap_ne
882 
        pla
883 
        cmp_flag $ff    ;returned all flags on?
884 
        trap_ne
885 
        tsx
886 
        cpx #$ff        ;sp after php?
887 
        trap_ne
888 
        set_stat 0      ;all off
889 
        trap_mi         ;branches should not be taken
890 
        trap_vs
891 
        trap_cs
892 
        trap_eq
893 
        bpl br11        ;branches should be taken
894 
        trap
895 
br11    bvc br12
896 
        trap
897 
br12    bcc br13
898 
        trap
899 
br13    bne br14
900 
        trap
901 
br14    php
902 
        pla
903 
        cmp_flag 0      ;flags off except break (pushed by sw) + reserved?
904 
        trap_ne
905 
        ;crosscheck flags
906 
        set_stat carry
907 
        trap_cc
908 
        set_stat zero
909 
        trap_ne
910 
        set_stat overfl
911 
        trap_vc
912 
        set_stat minus
913 
        trap_pl
914 
        set_stat $ff-carry
915 
        trap_cs
916 
        set_stat $ff-zero
917 
        trap_eq
918 
        set_stat $ff-overfl
919 
        trap_vs
920 
        set_stat $ff-minus
921 
        trap_mi
922 
 
923 
; partial pretest EOR #
924 
        set_a $3c,0
925 
        eor #$c3
926 
        tst_a $ff,fn
927 
        set_a $c3,0
928 
        eor #$c3
929 
        tst_a 0,fz
930 
 
931 
; PC modifying instructions except branches (NOP, JMP, JSR, RTS, BRK, RTI)
932 
; testing NOP
933 
        ldx #$24
934 
        ldy #$42
935 
        set_a $18,0
936 
        nop
937 
        tst_a $18,0
938 
        cpx #$24
939 
        trap_ne
940 
        cpy #$42
941 
        trap_ne
942 
        ldx #$db
943 
        ldy #$bd
944 
        set_a $e7,$ff
945 
        nop
946 
        tst_a $e7,$ff
947 
        cpx #$db
948 
        trap_ne
949 
        cpy #$bd
950 
        trap_ne
951 
 
952 
; jump absolute
953 
        set_stat $0
954 
        lda #'F'
955 
        ldx #'A'
956 
        ldy #'R'        ;N=0, V=0, Z=0, C=0
957 
        jmp test_far
958 
        nop
959 
        nop
960 
        trap_ne         ;runover protection
961 
        inx
962 
        inx
963 
far_ret
964 
        trap_eq         ;returned flags OK?
965 
        trap_pl
966 
        trap_cc
967 
        trap_vc
968 
        cmp #('F'^$aa)  ;returned registers OK?
969 
        trap_ne
970 
        cpx #('A'+1)
971 
        trap_ne
972 
        cpy #('R'-3)
973 
        trap_ne
974 
        dex
975 
        iny
976 
        iny
977 
        iny
978 
        eor #$aa        ;N=0, V=1, Z=0, C=1
979 
        jmp test_near
980 
        nop
981 
        nop
982 
        trap_ne         ;runover protection
983 
        inx
984 
        inx
985 
test_near
986 
        trap_eq         ;passed flags OK?
987 
        trap_mi
988 
        trap_cc
989 
        trap_vc
990 
        cmp #'F'        ;passed registers OK?
991 
        trap_ne
992 
        cpx #'A'
993 
        trap_ne
994 
        cpy #'R'
995 
        trap_ne
996 
 
997 
; jump indirect
998 
        set_stat 0
999 
        lda #'I'
1000 
        ldx #'N'
1001 
        ldy #'D'        ;N=0, V=0, Z=0, C=0
1002 
        jmp (ptr_tst_ind)
1003 
        nop
1004 
        trap_ne         ;runover protection
1005 
        dey
1006 
        dey
1007 
ind_ret
1008 
        php             ;either SP or Y count will fail, if we do not hit
1009 
        dey
1010 
        dey
1011 
        dey
1012 
        plp
1013 
        trap_eq         ;returned flags OK?
1014 
        trap_pl
1015 
        trap_cc
1016 
        trap_vc
1017 
        cmp #('I'^$aa)  ;returned registers OK?
1018 
        trap_ne
1019 
        cpx #('N'+1)
1020 
        trap_ne
1021 
        cpy #('D'-6)
1022 
        trap_ne
1023 
        tsx             ;SP check
1024 
        cpx #$ff
1025 
        trap_ne
1026 
 
1027 
; jump subroutine & return from subroutine
1028 
        set_stat 0
1029 
        lda #'J'
1030 
        ldx #'S'
1031 
        ldy #'R'        ;N=0, V=0, Z=0, C=0
1032 
        jsr test_jsr
1033 
jsr_ret = *-1           ;last address of jsr = return address
1034 
        php             ;either SP or Y count will fail, if we do not hit
1035 
        dey
1036 
        dey
1037 
        dey
1038 
        plp
1039 
        trap_eq         ;returned flags OK?
1040 
        trap_pl
1041 
        trap_cc
1042 
        trap_vc
1043 
        cmp #('J'^$aa)  ;returned registers OK?
1044 
        trap_ne
1045 
        cpx #('S'+1)
1046 
        trap_ne
1047 
        cpy #('R'-6)
1048 
        trap_ne
1049 
        tsx             ;sp?
1050 
        cpx #$ff
1051 
        trap_ne
1052 
 
1053 
; break & return from interrupt
1054 
    if ROM_vectors = 1
1055 
        set_stat 0
1056 
        lda #'B'
1057 
        ldx #'R'
1058 
        ldy #'K'        ;N=0, V=0, Z=0, C=0
1059 
        brk
1060 
    else
1061 
        lda #hi brk_ret ;emulated break
1062 
        pha
1063 
        lda #lo brk_ret
1064 
        pha
1065 
        lda #fao        ;set break & unused on stack
1066 
        pha
1067 
        set_stat intdis
1068 
        lda #'B'
1069 
        ldx #'R'
1070 
        ldy #'K'        ;N=0, V=0, Z=0, C=0
1071 
        jmp irq_trap
1072 
    endif
1073 
        dey             ;should not be executed
1074 
brk_ret                 ;address of break return
1075 
        php             ;either SP or Y count will fail, if we do not hit
1076 
        dey
1077 
        dey
1078 
        dey
1079 
        cmp #('B'^$aa)  ;returned registers OK?
1080 
        trap_ne
1081 
        cpx #('R'+1)
1082 
        trap_ne
1083 
        cpy #('K'-6)
1084 
        trap_ne
1085 
        pla             ;returned flags OK (unchanged)?
1086 
        cmp_flag 0
1087 
        trap_ne
1088 
        tsx             ;sp?
1089 
        cpx #$ff
1090 
        trap_ne
1091 
 
1092 
; test set and clear flags CLC CLI CLD CLV SEC SEI SED
1093 
        set_stat $ff
1094 
        clc
1095 
        tst_stat $ff-carry
1096 
        sec
1097 
        tst_stat $ff
1098 
    if I_flag = 3
1099 
        cli
1100 
        tst_stat $ff-intdis
1101 
        sei
1102 
        tst_stat $ff
1103 
    endif
1104 
        cld
1105 
        tst_stat $ff-decmode
1106 
        sed
1107 
        tst_stat $ff
1108 
        clv
1109 
        tst_stat $ff-overfl
1110 
        set_stat 0
1111 
        tst_stat 0
1112 
        sec
1113 
        tst_stat carry
1114 
        clc
1115 
        tst_stat 0
1116 
    if I_flag = 3
1117 
        sei
1118 
        tst_stat intdis
1119 
        cli
1120 
        tst_stat 0
1121 
    endif
1122 
        sed
1123 
        tst_stat decmode
1124 
        cld
1125 
        tst_stat 0
1126 
        set_stat overfl
1127 
        tst_stat overfl
1128 
        clv
1129 
        tst_stat 0
1130 
; testing index register increment/decrement and transfer
1131 
; INX INY DEX DEY TAX TXA TAY TYA
1132 
        ldx #$fe
1133 
        set_stat $ff
1134 
        inx             ;ff
1135 
        tst_x $ff,$ff-zero
1136 
        inx             ;00
1137 
        tst_x 0,$ff-minus
1138 
        inx             ;01
1139 
        tst_x 1,$ff-minus-zero
1140 
        dex             ;00
1141 
        tst_x 0,$ff-minus
1142 
        dex             ;ff
1143 
        tst_x $ff,$ff-zero
1144 
        dex             ;fe
1145 
        set_stat 0
1146 
        inx             ;ff
1147 
        tst_x $ff,minus
1148 
        inx             ;00
1149 
        tst_x 0,zero
1150 
        inx             ;01
1151 
        tst_x 1,0
1152 
        dex             ;00
1153 
        tst_x 0,zero
1154 
        dex             ;ff
1155 
        tst_x $ff,minus
1156 
 
1157 
        ldy #$fe
1158 
        set_stat $ff
1159 
        iny             ;ff
1160 
        tst_y $ff,$ff-zero
1161 
        iny             ;00
1162 
        tst_y 0,$ff-minus
1163 
        iny             ;01
1164 
        tst_y 1,$ff-minus-zero
1165 
        dey             ;00
1166 
        tst_y 0,$ff-minus
1167 
        dey             ;ff
1168 
        tst_y $ff,$ff-zero
1169 
        dey             ;fe
1170 
        set_stat 0
1171 
        iny             ;ff
1172 
        tst_y $ff,0+minus
1173 
        iny             ;00
1174 
        tst_y 0,zero
1175 
        iny             ;01
1176 
        tst_y 1,0
1177 
        dey             ;00
1178 
        tst_y 0,zero
1179 
        dey             ;ff
1180 
        tst_y $ff,minus
1181 
 
1182 
        ldx #$ff
1183 
        set_stat $ff
1184 
        txa
1185 
        tst_a $ff,$ff-zero
1186 
        php
1187 
        inx             ;00
1188 
        plp
1189 
        txa
1190 
        tst_a 0,$ff-minus
1191 
        php
1192 
        inx             ;01
1193 
        plp
1194 
        txa
1195 
        tst_a 1,$ff-minus-zero
1196 
        set_stat 0
1197 
        txa
1198 
        tst_a 1,0
1199 
        php
1200 
        dex             ;00
1201 
        plp
1202 
        txa
1203 
        tst_a 0,zero
1204 
        php
1205 
        dex             ;ff
1206 
        plp
1207 
        txa
1208 
        tst_a $ff,minus
1209 
 
1210 
        ldy #$ff
1211 
        set_stat $ff
1212 
        tya
1213 
        tst_a $ff,$ff-zero
1214 
        php
1215 
        iny             ;00
1216 
        plp
1217 
        tya
1218 
        tst_a 0,$ff-minus
1219 
        php
1220 
        iny             ;01
1221 
        plp
1222 
        tya
1223 
        tst_a 1,$ff-minus-zero
1224 
        set_stat 0
1225 
        tya
1226 
        tst_a 1,0
1227 
        php
1228 
        dey             ;00
1229 
        plp
1230 
        tya
1231 
        tst_a 0,zero
1232 
        php
1233 
        dey             ;ff
1234 
        plp
1235 
        tya
1236 
        tst_a $ff,minus
1237 
 
1238 
        load_flag $ff
1239 
        pha
1240 
        ldx #$ff        ;ff
1241 
        txa
1242 
        plp
1243 
        tay
1244 
        tst_y $ff,$ff-zero
1245 
        php
1246 
        inx             ;00
1247 
        txa
1248 
        plp
1249 
        tay
1250 
        tst_y 0,$ff-minus
1251 
        php
1252 
        inx             ;01
1253 
        txa
1254 
        plp
1255 
        tay
1256 
        tst_y 1,$ff-minus-zero
1257 
        load_flag 0
1258 
        pha
1259 
        lda #0
1260 
        txa
1261 
        plp
1262 
        tay
1263 
        tst_y 1,0
1264 
        php
1265 
        dex             ;00
1266 
        txa
1267 
        plp
1268 
        tay
1269 
        tst_y 0,zero
1270 
        php
1271 
        dex             ;ff
1272 
        txa
1273 
        plp
1274 
        tay
1275 
        tst_y $ff,minus
1276 
 
1277 
 
1278 
        load_flag $ff
1279 
        pha
1280 
        ldy #$ff        ;ff
1281 
        tya
1282 
        plp
1283 
        tax
1284 
        tst_x $ff,$ff-zero
1285 
        php
1286 
        iny             ;00
1287 
        tya
1288 
        plp
1289 
        tax
1290 
        tst_x 0,$ff-minus
1291 
        php
1292 
        iny             ;01
1293 
        tya
1294 
        plp
1295 
        tax
1296 
        tst_x 1,$ff-minus-zero
1297 
        load_flag 0
1298 
        pha
1299 
        lda #0          ;preset status
1300 
        tya
1301 
        plp
1302 
        tax
1303 
        tst_x 1,0
1304 
        php
1305 
        dey             ;00
1306 
        tya
1307 
        plp
1308 
        tax
1309 
        tst_x 0,zero
1310 
        php
1311 
        dey             ;ff
1312 
        tya
1313 
        plp
1314 
        tax
1315 
        tst_x $ff,minus
1316 
 
1317 
;TSX sets NZ - TXS does not
1318 
        ldx #1          ;01
1319 
        set_stat $ff
1320 
        txs
1321 
        php
1322 
        lda $101
1323 
        cmp_flag $ff
1324 
        trap_ne
1325 
        set_stat 0
1326 
        txs
1327 
        php
1328 
        lda $101
1329 
        cmp_flag 0
1330 
        trap_ne
1331 
        dex             ;00
1332 
        set_stat $ff
1333 
        txs
1334 
        php
1335 
        lda $100
1336 
        cmp_flag $ff
1337 
        trap_ne
1338 
        set_stat 0
1339 
        txs
1340 
        php
1341 
        lda $100
1342 
        cmp_flag 0
1343 
        trap_ne
1344 
        dex             ;ff
1345 
        set_stat $ff
1346 
        txs
1347 
        php
1348 
        lda $1ff
1349 
        cmp_flag $ff
1350 
        trap_ne
1351 
        set_stat 0
1352 
        txs
1353 
        php
1354 
        lda $1ff
1355 
        cmp_flag 0
1356 
 
1357 
        ldx #1
1358 
        txs             ;sp=01
1359 
        set_stat $ff
1360 
        tsx             ;clears Z, N
1361 
        php             ;sp=00
1362 
        cpx #1
1363 
        trap_ne
1364 
        lda $101
1365 
        cmp_flag $ff-minus-zero
1366 
        trap_ne
1367 
        set_stat $ff
1368 
        tsx             ;clears N, sets Z
1369 
        php             ;sp=ff
1370 
        cpx #0
1371 
        trap_ne
1372 
        lda $100
1373 
        cmp_flag $ff-minus
1374 
        trap_ne
1375 
        set_stat $ff
1376 
        tsx             ;clears N, sets Z
1377 
        php             ;sp=fe
1378 
        cpx #$ff
1379 
        trap_ne
1380 
        lda $1ff
1381 
        cmp_flag $ff-zero
1382 
        trap_ne
1383 
 
1384 
        ldx #1
1385 
        txs             ;sp=01
1386 
        set_stat 0
1387 
        tsx             ;clears Z, N
1388 
        php             ;sp=00
1389 
        cpx #1
1390 
        trap_ne
1391 
        lda $101
1392 
        cmp_flag 0
1393 
        trap_ne
1394 
        set_stat 0
1395 
        tsx             ;clears N, sets Z
1396 
        php             ;sp=ff
1397 
        cpx #0
1398 
        trap_ne
1399 
        lda $100
1400 
        cmp_flag zero
1401 
        trap_ne
1402 
        set_stat 0
1403 
        tsx             ;clears N, sets Z
1404 
        php             ;sp=fe
1405 
        cpx #$ff
1406 
        trap_ne
1407 
        lda $1ff
1408 
        cmp_flag minus
1409 
        trap_ne
1410 
        pla             ;sp=ff
1411 
 
1412 
; testing index register load & store LDY LDX STY STX all addressing modes
1413 
; LDX / STX - zp,y / abs,y
1414 
        ldy #3
1415 
tldx
1416 
        set_stat 0
1417 
        ldx zp1,y
1418 
        php         ;test stores do not alter flags
1419 
        txa
1420 
        eor #$c3
1421 
        plp
1422 
        sta abst,y
1423 
        php         ;flags after load/store sequence
1424 
        eor #$c3
1425 
        cmp abs1,y  ;test result
1426 
        trap_ne
1427 
        pla         ;load status
1428 
        eor_flag 0
1429 
        cmp fLDx,y  ;test flags
1430 
        trap_ne
1431 
        dey
1432 
        bpl tldx
1433 
 
1434 
        ldy #3
1435 
tldx1
1436 
        set_stat $ff
1437 
        ldx zp1,y
1438 
        php         ;test stores do not alter flags
1439 
        txa
1440 
        eor #$c3
1441 
        plp
1442 
        sta abst,y
1443 
        php         ;flags after load/store sequence
1444 
        eor #$c3
1445 
        cmp abs1,y  ;test result
1446 
        trap_ne
1447 
        pla         ;load status
1448 
        eor_flag lo~fnz ;mask bits not altered
1449 
        cmp fLDx,y  ;test flags
1450 
        trap_ne
1451 
        dey
1452 
        bpl tldx1
1453 
 
1454 
        ldy #3
1455 
tldx2
1456 
        set_stat 0
1457 
        ldx abs1,y
1458 
        php         ;test stores do not alter flags
1459 
        txa
1460 
        eor #$c3
1461 
        tax
1462 
        plp
1463 
        stx zpt,y
1464 
        php         ;flags after load/store sequence
1465 
        eor #$c3
1466 
        cmp zp1,y   ;test result
1467 
        trap_ne
1468 
        pla         ;load status
1469 
        eor_flag 0
1470 
        cmp fLDx,y  ;test flags
1471 
        trap_ne
1472 
        dey
1473 
        bpl tldx2
1474 
 
1475 
        ldy #3
1476 
tldx3
1477 
        set_stat $ff
1478 
        ldx abs1,y
1479 
        php         ;test stores do not alter flags
1480 
        txa
1481 
        eor #$c3
1482 
        tax
1483 
        plp
1484 
        stx zpt,y
1485 
        php         ;flags after load/store sequence
1486 
        eor #$c3
1487 
        cmp zp1,y   ;test result
1488 
        trap_ne
1489 
        pla         ;load status
1490 
        eor_flag lo~fnz ;mask bits not altered
1491 
        cmp fLDx,y  ;test flags
1492 
        trap_ne
1493 
        dey
1494 
        bpl tldx3
1495 
 
1496 
        ldy #3      ;testing store result
1497 
        ldx #0
1498 
tstx    lda zpt,y
1499 
        eor #$c3
1500 
        cmp zp1,y
1501 
        trap_ne     ;store to zp data
1502 
        stx zpt,y   ;clear
1503 
        lda abst,y
1504 
        eor #$c3
1505 
        cmp abs1,y
1506 
        trap_ne     ;store to abs data
1507 
        txa
1508 
        sta abst,y  ;clear
1509 
        dey
1510 
        bpl tstx
1511 
 
1512 
; indexed wraparound test (only zp should wrap)
1513 
        ldy #3+$fa
1514 
tldx4   ldx zp1-$fa&$ff,y   ;wrap on indexed zp
1515 
        txa
1516 
        sta abst-$fa,y      ;no STX abs,y!
1517 
        dey
1518 
        cpy #$fa
1519 
        bcs tldx4
1520 
        ldy #3+$fa
1521 
tldx5   ldx abs1-$fa,y      ;no wrap on indexed abs
1522 
        stx zpt-$fa&$ff,y
1523 
        dey
1524 
        cpy #$fa
1525 
        bcs tldx5
1526 
        ldy #3      ;testing wraparound result
1527 
        ldx #0
1528 
tstx1   lda zpt,y
1529 
        cmp zp1,y
1530 
        trap_ne     ;store to zp data
1531 
        stx zpt,y   ;clear
1532 
        lda abst,y
1533 
        cmp abs1,y
1534 
        trap_ne     ;store to abs data
1535 
        txa
1536 
        sta abst,y  ;clear
1537 
        dey
1538 
        bpl tstx1
1539 
 
1540 
; LDY / STY - zp,x / abs,x
1541 
        ldx #3
1542 
tldy
1543 
        set_stat 0
1544 
        ldy zp1,x
1545 
        php         ;test stores do not alter flags
1546 
        tya
1547 
        eor #$c3
1548 
        plp
1549 
        sta abst,x
1550 
        php         ;flags after load/store sequence
1551 
        eor #$c3
1552 
        cmp abs1,x  ;test result
1553 
        trap_ne
1554 
        pla         ;load status
1555 
        eor_flag 0
1556 
        cmp fLDx,x  ;test flags
1557 
        trap_ne
1558 
        dex
1559 
        bpl tldy
1560 
 
1561 
        ldx #3
1562 
tldy1
1563 
        set_stat $ff
1564 
        ldy zp1,x
1565 
        php         ;test stores do not alter flags
1566 
        tya
1567 
        eor #$c3
1568 
        plp
1569 
        sta abst,x
1570 
        php         ;flags after load/store sequence
1571 
        eor #$c3
1572 
        cmp abs1,x  ;test result
1573 
        trap_ne
1574 
        pla         ;load status
1575 
        eor_flag lo~fnz ;mask bits not altered
1576 
        cmp fLDx,x  ;test flags
1577 
        trap_ne
1578 
        dex
1579 
        bpl tldy1
1580 
 
1581 
        ldx #3
1582 
tldy2
1583 
        set_stat 0
1584 
        ldy abs1,x
1585 
        php         ;test stores do not alter flags
1586 
        tya
1587 
        eor #$c3
1588 
        tay
1589 
        plp
1590 
        sty zpt,x
1591 
        php         ;flags after load/store sequence
1592 
        eor #$c3
1593 
        cmp zp1,x   ;test result
1594 
        trap_ne
1595 
        pla         ;load status
1596 
        eor_flag 0
1597 
        cmp fLDx,x  ;test flags
1598 
        trap_ne
1599 
        dex
1600 
        bpl tldy2
1601 
 
1602 
        ldx #3
1603 
tldy3
1604 
        set_stat $ff
1605 
        ldy abs1,x
1606 
        php         ;test stores do not alter flags
1607 
        tya
1608 
        eor #$c3
1609 
        tay
1610 
        plp
1611 
        sty zpt,x
1612 
        php         ;flags after load/store sequence
1613 
        eor #$c3
1614 
        cmp zp1,x   ;test result
1615 
        trap_ne
1616 
        pla         ;load status
1617 
        eor_flag lo~fnz ;mask bits not altered
1618 
        cmp fLDx,x  ;test flags
1619 
        trap_ne
1620 
        dex
1621 
        bpl tldy3
1622 
 
1623 
        ldx #3      ;testing store result
1624 
        ldy #0
1625 
tsty    lda zpt,x
1626 
        eor #$c3
1627 
        cmp zp1,x
1628 
        trap_ne     ;store to zp,x data
1629 
        sty zpt,x   ;clear
1630 
        lda abst,x
1631 
        eor #$c3
1632 
        cmp abs1,x
1633 
        trap_ne     ;store to abs,x data
1634 
        txa
1635 
        sta abst,x  ;clear
1636 
        dex
1637 
        bpl tsty
1638 
 
1639 
; indexed wraparound test (only zp should wrap)
1640 
        ldx #3+$fa
1641 
tldy4   ldy zp1-$fa&$ff,x   ;wrap on indexed zp
1642 
        tya
1643 
        sta abst-$fa,x      ;no STX abs,x!
1644 
        dex
1645 
        cpx #$fa
1646 
        bcs tldy4
1647 
        ldx #3+$fa
1648 
tldy5   ldy abs1-$fa,x      ;no wrap on indexed abs
1649 
        sty zpt-$fa&$ff,x
1650 
        dex
1651 
        cpx #$fa
1652 
        bcs tldy5
1653 
        ldx #3      ;testing wraparound result
1654 
        ldy #0
1655 
tsty1   lda zpt,x
1656 
        cmp zp1,x
1657 
        trap_ne     ;store to zp,x data
1658 
        sty zpt,x   ;clear
1659 
        lda abst,x
1660 
        cmp abs1,x
1661 
        trap_ne     ;store to abs,x data
1662 
        txa
1663 
        sta abst,x  ;clear
1664 
        dex
1665 
        bpl tsty1
1666 
 
1667 
; LDX / STX - zp / abs / #
1668 
        set_stat 0
1669 
        ldx zp1
1670 
        php         ;test stores do not alter flags
1671 
        txa
1672 
        eor #$c3
1673 
        tax
1674 
        plp
1675 
        stx abst
1676 
        php         ;flags after load/store sequence
1677 
        eor #$c3
1678 
        tax
1679 
        cpx #$c3    ;test result
1680 
        trap_ne
1681 
        pla         ;load status
1682 
        eor_flag 0
1683 
        cmp fLDx    ;test flags
1684 
        trap_ne
1685 
        set_stat 0
1686 
        ldx zp1+1
1687 
        php         ;test stores do not alter flags
1688 
        txa
1689 
        eor #$c3
1690 
        tax
1691 
        plp
1692 
        stx abst+1
1693 
        php         ;flags after load/store sequence
1694 
        eor #$c3
1695 
        tax
1696 
        cpx #$82    ;test result
1697 
        trap_ne
1698 
        pla         ;load status
1699 
        eor_flag 0
1700 
        cmp fLDx+1  ;test flags
1701 
        trap_ne
1702 
        set_stat 0
1703 
        ldx zp1+2
1704 
        php         ;test stores do not alter flags
1705 
        txa
1706 
        eor #$c3
1707 
        tax
1708 
        plp
1709 
        stx abst+2
1710 
        php         ;flags after load/store sequence
1711 
        eor #$c3
1712 
        tax
1713 
        cpx #$41    ;test result
1714 
        trap_ne
1715 
        pla         ;load status
1716 
        eor_flag 0
1717 
        cmp fLDx+2  ;test flags
1718 
        trap_ne
1719 
        set_stat 0
1720 
        ldx zp1+3
1721 
        php         ;test stores do not alter flags
1722 
        txa
1723 
        eor #$c3
1724 
        tax
1725 
        plp
1726 
        stx abst+3
1727 
        php         ;flags after load/store sequence
1728 
        eor #$c3
1729 
        tax
1730 
        cpx #0      ;test result
1731 
        trap_ne
1732 
        pla         ;load status
1733 
        eor_flag 0
1734 
        cmp fLDx+3  ;test flags
1735 
        trap_ne
1736 
 
1737 
        set_stat $ff
1738 
        ldx zp1
1739 
        php         ;test stores do not alter flags
1740 
        txa
1741 
        eor #$c3
1742 
        tax
1743 
        plp
1744 
        stx abst
1745 
        php         ;flags after load/store sequence
1746 
        eor #$c3
1747 
        tax
1748 
        cpx #$c3    ;test result
1749 
        trap_ne     ;
1750 
        pla         ;load status
1751 
        eor_flag lo~fnz ;mask bits not altered
1752 
        cmp fLDx    ;test flags
1753 
        trap_ne
1754 
        set_stat $ff
1755 
        ldx zp1+1
1756 
        php         ;test stores do not alter flags
1757 
        txa
1758 
        eor #$c3
1759 
        tax
1760 
        plp
1761 
        stx abst+1
1762 
        php         ;flags after load/store sequence
1763 
        eor #$c3
1764 
        tax
1765 
        cpx #$82    ;test result
1766 
        trap_ne
1767 
        pla         ;load status
1768 
        eor_flag lo~fnz ;mask bits not altered
1769 
        cmp fLDx+1  ;test flags
1770 
        trap_ne
1771 
        set_stat $ff
1772 
        ldx zp1+2
1773 
        php         ;test stores do not alter flags
1774 
        txa
1775 
        eor #$c3
1776 
        tax
1777 
        plp
1778 
        stx abst+2
1779 
        php         ;flags after load/store sequence
1780 
        eor #$c3
1781 
        tax
1782 
        cpx #$41    ;test result
1783 
        trap_ne     ;
1784 
        pla         ;load status
1785 
        eor_flag lo~fnz ;mask bits not altered
1786 
        cmp fLDx+2  ;test flags
1787 
        trap_ne
1788 
        set_stat $ff
1789 
        ldx zp1+3
1790 
        php         ;test stores do not alter flags
1791 
        txa
1792 
        eor #$c3
1793 
        tax
1794 
        plp
1795 
        stx abst+3
1796 
        php         ;flags after load/store sequence
1797 
        eor #$c3
1798 
        tax
1799 
        cpx #0      ;test result
1800 
        trap_ne
1801 
        pla         ;load status
1802 
        eor_flag lo~fnz ;mask bits not altered
1803 
        cmp fLDx+3  ;test flags
1804 
        trap_ne
1805 
 
1806 
        set_stat 0
1807 
        ldx abs1
1808 
        php         ;test stores do not alter flags
1809 
        txa
1810 
        eor #$c3
1811 
        tax
1812 
        plp
1813 
        stx zpt
1814 
        php         ;flags after load/store sequence
1815 
        eor #$c3
1816 
        cmp zp1     ;test result
1817 
        trap_ne
1818 
        pla         ;load status
1819 
        eor_flag 0
1820 
        cmp fLDx    ;test flags
1821 
        trap_ne
1822 
        set_stat 0
1823 
        ldx abs1+1
1824 
        php         ;test stores do not alter flags
1825 
        txa
1826 
        eor #$c3
1827 
        tax
1828 
        plp
1829 
        stx zpt+1
1830 
        php         ;flags after load/store sequence
1831 
        eor #$c3
1832 
        cmp zp1+1   ;test result
1833 
        trap_ne
1834 
        pla         ;load status
1835 
        eor_flag 0
1836 
        cmp fLDx+1  ;test flags
1837 
        trap_ne
1838 
        set_stat 0
1839 
        ldx abs1+2
1840 
        php         ;test stores do not alter flags
1841 
        txa
1842 
        eor #$c3
1843 
        tax
1844 
        plp
1845 
        stx zpt+2
1846 
        php         ;flags after load/store sequence
1847 
        eor #$c3
1848 
        cmp zp1+2   ;test result
1849 
        trap_ne
1850 
        pla         ;load status
1851 
        eor_flag 0
1852 
        cmp fLDx+2  ;test flags
1853 
        trap_ne
1854 
        set_stat 0
1855 
        ldx abs1+3
1856 
        php         ;test stores do not alter flags
1857 
        txa
1858 
        eor #$c3
1859 
        tax
1860 
        plp
1861 
        stx zpt+3
1862 
        php         ;flags after load/store sequence
1863 
        eor #$c3
1864 
        cmp zp1+3   ;test result
1865 
        trap_ne
1866 
        pla         ;load status
1867 
        eor_flag 0
1868 
        cmp fLDx+3  ;test flags
1869 
        trap_ne
1870 
 
1871 
        set_stat $ff
1872 
        ldx abs1
1873 
        php         ;test stores do not alter flags
1874 
        txa
1875 
        eor #$c3
1876 
        tax
1877 
        plp
1878 
        stx zpt
1879 
        php         ;flags after load/store sequence
1880 
        eor #$c3
1881 
        tax
1882 
        cpx zp1     ;test result
1883 
        trap_ne
1884 
        pla         ;load status
1885 
        eor_flag lo~fnz ;mask bits not altered
1886 
        cmp fLDx    ;test flags
1887 
        trap_ne
1888 
        set_stat $ff
1889 
        ldx abs1+1
1890 
        php         ;test stores do not alter flags
1891 
        txa
1892 
        eor #$c3
1893 
        tax
1894 
        plp
1895 
        stx zpt+1
1896 
        php         ;flags after load/store sequence
1897 
        eor #$c3
1898 
        tax
1899 
        cpx zp1+1   ;test result
1900 
        trap_ne
1901 
        pla         ;load status
1902 
        eor_flag lo~fnz ;mask bits not altered
1903 
        cmp fLDx+1  ;test flags
1904 
        trap_ne
1905 
        set_stat $ff
1906 
        ldx abs1+2
1907 
        php         ;test stores do not alter flags
1908 
        txa
1909 
        eor #$c3
1910 
        tax
1911 
        plp
1912 
        stx zpt+2
1913 
        php         ;flags after load/store sequence
1914 
        eor #$c3
1915 
        tax
1916 
        cpx zp1+2   ;test result
1917 
        trap_ne
1918 
        pla         ;load status
1919 
        eor_flag lo~fnz ;mask bits not altered
1920 
        cmp fLDx+2  ;test flags
1921 
        trap_ne
1922 
        set_stat $ff
1923 
        ldx abs1+3
1924 
        php         ;test stores do not alter flags
1925 
        txa
1926 
        eor #$c3
1927 
        tax
1928 
        plp
1929 
        stx zpt+3
1930 
        php         ;flags after load/store sequence
1931 
        eor #$c3
1932 
        tax
1933 
        cpx zp1+3   ;test result
1934 
        trap_ne
1935 
        pla         ;load status
1936 
        eor_flag lo~fnz ;mask bits not altered
1937 
        cmp fLDx+3  ;test flags
1938 
        trap_ne
1939 
 
1940 
        set_stat 0
1941 
        ldx #$c3
1942 
        php
1943 
        cpx abs1    ;test result
1944 
        trap_ne
1945 
        pla         ;load status
1946 
        eor_flag 0
1947 
        cmp fLDx    ;test flags
1948 
        trap_ne
1949 
        set_stat 0
1950 
        ldx #$82
1951 
        php
1952 
        cpx abs1+1  ;test result
1953 
        trap_ne
1954 
        pla         ;load status
1955 
        eor_flag 0
1956 
        cmp fLDx+1  ;test flags
1957 
        trap_ne
1958 
        set_stat 0
1959 
        ldx #$41
1960 
        php
1961 
        cpx abs1+2  ;test result
1962 
        trap_ne
1963 
        pla         ;load status
1964 
        eor_flag 0
1965 
        cmp fLDx+2  ;test flags
1966 
        trap_ne
1967 
        set_stat 0
1968 
        ldx #0
1969 
        php
1970 
        cpx abs1+3  ;test result
1971 
        trap_ne
1972 
        pla         ;load status
1973 
        eor_flag 0
1974 
        cmp fLDx+3  ;test flags
1975 
        trap_ne
1976 
 
1977 
        set_stat $ff
1978 
        ldx #$c3
1979 
        php
1980 
        cpx abs1    ;test result
1981 
        trap_ne
1982 
        pla         ;load status
1983 
        eor_flag lo~fnz ;mask bits not altered
1984 
        cmp fLDx    ;test flags
1985 
        trap_ne
1986 
        set_stat $ff
1987 
        ldx #$82
1988 
        php
1989 
        cpx abs1+1  ;test result
1990 
        trap_ne
1991 
        pla         ;load status
1992 
        eor_flag lo~fnz ;mask bits not altered
1993 
        cmp fLDx+1  ;test flags
1994 
        trap_ne
1995 
        set_stat $ff
1996 
        ldx #$41
1997 
        php
1998 
        cpx abs1+2  ;test result
1999 
        trap_ne
2000 
        pla         ;load status
2001 
        eor_flag lo~fnz ;mask bits not altered
2002 
        cmp fLDx+2  ;test flags
2003 
        trap_ne
2004 
        set_stat $ff
2005 
        ldx #0
2006 
        php
2007 
        cpx abs1+3  ;test result
2008 
        trap_ne
2009 
        pla         ;load status
2010 
        eor_flag lo~fnz ;mask bits not altered
2011 
        cmp fLDx+3  ;test flags
2012 
        trap_ne
2013 
 
2014 
        ldx #0
2015 
        lda zpt
2016 
        eor #$c3
2017 
        cmp zp1
2018 
        trap_ne     ;store to zp data
2019 
        stx zpt     ;clear
2020 
        lda abst
2021 
        eor #$c3
2022 
        cmp abs1
2023 
        trap_ne     ;store to abs data
2024 
        stx abst    ;clear
2025 
        lda zpt+1
2026 
        eor #$c3
2027 
        cmp zp1+1
2028 
        trap_ne     ;store to zp data
2029 
        stx zpt+1   ;clear
2030 
        lda abst+1
2031 
        eor #$c3
2032 
        cmp abs1+1
2033 
        trap_ne     ;store to abs data
2034 
        stx abst+1  ;clear
2035 
        lda zpt+2
2036 
        eor #$c3
2037 
        cmp zp1+2
2038 
        trap_ne     ;store to zp data
2039 
        stx zpt+2   ;clear
2040 
        lda abst+2
2041 
        eor #$c3
2042 
        cmp abs1+2
2043 
        trap_ne     ;store to abs data
2044 
        stx abst+2  ;clear
2045 
        lda zpt+3
2046 
        eor #$c3
2047 
        cmp zp1+3
2048 
        trap_ne     ;store to zp data
2049 
        stx zpt+3   ;clear
2050 
        lda abst+3
2051 
        eor #$c3
2052 
        cmp abs1+3
2053 
        trap_ne     ;store to abs data
2054 
        stx abst+3  ;clear
2055 
 
2056 
; LDY / STY - zp / abs / #
2057 
        set_stat 0
2058 
        ldy zp1
2059 
        php         ;test stores do not alter flags
2060 
        tya
2061 
        eor #$c3
2062 
        tay
2063 
        plp
2064 
        sty abst
2065 
        php         ;flags after load/store sequence
2066 
        eor #$c3
2067 
        tay
2068 
        cpy #$c3    ;test result
2069 
        trap_ne
2070 
        pla         ;load status
2071 
        eor_flag 0
2072 
        cmp fLDx    ;test flags
2073 
        trap_ne
2074 
        set_stat 0
2075 
        ldy zp1+1
2076 
        php         ;test stores do not alter flags
2077 
        tya
2078 
        eor #$c3
2079 
        tay
2080 
        plp
2081 
        sty abst+1
2082 
        php         ;flags after load/store sequence
2083 
        eor #$c3
2084 
        tay
2085 
        cpy #$82    ;test result
2086 
        trap_ne
2087 
        pla         ;load status
2088 
        eor_flag 0
2089 
        cmp fLDx+1  ;test flags
2090 
        trap_ne
2091 
        set_stat 0
2092 
        ldy zp1+2
2093 
        php         ;test stores do not alter flags
2094 
        tya
2095 
        eor #$c3
2096 
        tay
2097 
        plp
2098 
        sty abst+2
2099 
        php         ;flags after load/store sequence
2100 
        eor #$c3
2101 
        tay
2102 
        cpy #$41    ;test result
2103 
        trap_ne
2104 
        pla         ;load status
2105 
        eor_flag 0
2106 
        cmp fLDx+2  ;test flags
2107 
        trap_ne
2108 
        set_stat 0
2109 
        ldy zp1+3
2110 
        php         ;test stores do not alter flags
2111 
        tya
2112 
        eor #$c3
2113 
        tay
2114 
        plp
2115 
        sty abst+3
2116 
        php         ;flags after load/store sequence
2117 
        eor #$c3
2118 
        tay
2119 
        cpy #0      ;test result
2120 
        trap_ne
2121 
        pla         ;load status
2122 
        eor_flag 0
2123 
        cmp fLDx+3  ;test flags
2124 
        trap_ne
2125 
 
2126 
        set_stat $ff
2127 
        ldy zp1
2128 
        php         ;test stores do not alter flags
2129 
        tya
2130 
        eor #$c3
2131 
        tay
2132 
        plp
2133 
        sty abst
2134 
        php         ;flags after load/store sequence
2135 
        eor #$c3
2136 
        tay
2137 
        cpy #$c3    ;test result
2138 
        trap_ne
2139 
        pla         ;load status
2140 
        eor_flag lo~fnz ;mask bits not altered
2141 
        cmp fLDx    ;test flags
2142 
        trap_ne
2143 
        set_stat $ff
2144 
        ldy zp1+1
2145 
        php         ;test stores do not alter flags
2146 
        tya
2147 
        eor #$c3
2148 
        tay
2149 
        plp
2150 
        sty abst+1
2151 
        php         ;flags after load/store sequence
2152 
        eor #$c3
2153 
        tay
2154 
        cpy #$82   ;test result
2155 
        trap_ne
2156 
        pla         ;load status
2157 
        eor_flag lo~fnz ;mask bits not altered
2158 
        cmp fLDx+1  ;test flags
2159 
        trap_ne
2160 
        set_stat $ff
2161 
        ldy zp1+2
2162 
        php         ;test stores do not alter flags
2163 
        tya
2164 
        eor #$c3
2165 
        tay
2166 
        plp
2167 
        sty abst+2
2168 
        php         ;flags after load/store sequence
2169 
        eor #$c3
2170 
        tay
2171 
        cpy #$41    ;test result
2172 
        trap_ne
2173 
        pla         ;load status
2174 
        eor_flag lo~fnz ;mask bits not altered
2175 
        cmp fLDx+2  ;test flags
2176 
        trap_ne
2177 
        set_stat $ff
2178 
        ldy zp1+3
2179 
        php         ;test stores do not alter flags
2180 
        tya
2181 
        eor #$c3
2182 
        tay
2183 
        plp
2184 
        sty abst+3
2185 
        php         ;flags after load/store sequence
2186 
        eor #$c3
2187 
        tay
2188 
        cpy #0      ;test result
2189 
        trap_ne
2190 
        pla         ;load status
2191 
        eor_flag lo~fnz ;mask bits not altered
2192 
        cmp fLDx+3  ;test flags
2193 
        trap_ne
2194 
 
2195 
        set_stat 0
2196 
        ldy abs1
2197 
        php         ;test stores do not alter flags
2198 
        tya
2199 
        eor #$c3
2200 
        tay
2201 
        plp
2202 
        sty zpt
2203 
        php         ;flags after load/store sequence
2204 
        eor #$c3
2205 
        tay
2206 
        cpy zp1     ;test result
2207 
        trap_ne
2208 
        pla         ;load status
2209 
        eor_flag 0
2210 
        cmp fLDx    ;test flags
2211 
        trap_ne
2212 
        set_stat 0
2213 
        ldy abs1+1
2214 
        php         ;test stores do not alter flags
2215 
        tya
2216 
        eor #$c3
2217 
        tay
2218 
        plp
2219 
        sty zpt+1
2220 
        php         ;flags after load/store sequence
2221 
        eor #$c3
2222 
        tay
2223 
        cpy zp1+1   ;test result
2224 
        trap_ne
2225 
        pla         ;load status
2226 
        eor_flag 0
2227 
        cmp fLDx+1  ;test flags
2228 
        trap_ne
2229 
        set_stat 0
2230 
        ldy abs1+2
2231 
        php         ;test stores do not alter flags
2232 
        tya
2233 
        eor #$c3
2234 
        tay
2235 
        plp
2236 
        sty zpt+2
2237 
        php         ;flags after load/store sequence
2238 
        eor #$c3
2239 
        tay
2240 
        cpy zp1+2   ;test result
2241 
        trap_ne
2242 
        pla         ;load status
2243 
        eor_flag 0
2244 
        cmp fLDx+2  ;test flags
2245 
        trap_ne
2246 
        set_stat 0
2247 
        ldy abs1+3
2248 
        php         ;test stores do not alter flags
2249 
        tya
2250 
        eor #$c3
2251 
        tay
2252 
        plp
2253 
        sty zpt+3
2254 
        php         ;flags after load/store sequence
2255 
        eor #$c3
2256 
        tay
2257 
        cpy zp1+3   ;test result
2258 
        trap_ne
2259 
        pla         ;load status
2260 
        eor_flag 0
2261 
        cmp fLDx+3  ;test flags
2262 
        trap_ne
2263 
 
2264 
        set_stat $ff
2265 
        ldy abs1
2266 
        php         ;test stores do not alter flags
2267 
        tya
2268 
        eor #$c3
2269 
        tay
2270 
        plp
2271 
        sty zpt
2272 
        php         ;flags after load/store sequence
2273 
        eor #$c3
2274 
        tay
2275 
        cmp zp1     ;test result
2276 
        trap_ne
2277 
        pla         ;load status
2278 
        eor_flag lo~fnz ;mask bits not altered
2279 
        cmp fLDx    ;test flags
2280 
        trap_ne
2281 
        set_stat $ff
2282 
        ldy abs1+1
2283 
        php         ;test stores do not alter flags
2284 
        tya
2285 
        eor #$c3
2286 
        tay
2287 
        plp
2288 
        sty zpt+1
2289 
        php         ;flags after load/store sequence
2290 
        eor #$c3
2291 
        tay
2292 
        cmp zp1+1   ;test result
2293 
        trap_ne
2294 
        pla         ;load status
2295 
        eor_flag lo~fnz ;mask bits not altered
2296 
        cmp fLDx+1  ;test flags
2297 
        trap_ne
2298 
        set_stat $ff
2299 
        ldy abs1+2
2300 
        php         ;test stores do not alter flags
2301 
        tya
2302 
        eor #$c3
2303 
        tay
2304 
        plp
2305 
        sty zpt+2
2306 
        php         ;flags after load/store sequence
2307 
        eor #$c3
2308 
        tay
2309 
        cmp zp1+2   ;test result
2310 
        trap_ne
2311 
        pla         ;load status
2312 
        eor_flag lo~fnz ;mask bits not altered
2313 
        cmp fLDx+2  ;test flags
2314 
        trap_ne
2315 
        set_stat $ff
2316 
        ldy abs1+3
2317 
        php         ;test stores do not alter flags
2318 
        tya
2319 
        eor #$c3
2320 
        tay
2321 
        plp
2322 
        sty zpt+3
2323 
        php         ;flags after load/store sequence
2324 
        eor #$c3
2325 
        tay
2326 
        cmp zp1+3   ;test result
2327 
        trap_ne
2328 
        pla         ;load status
2329 
        eor_flag lo~fnz ;mask bits not altered
2330 
        cmp fLDx+3  ;test flags
2331 
        trap_ne
2332 
 
2333 
 
2334 
        set_stat 0
2335 
        ldy #$c3
2336 
        php
2337 
        cpy abs1    ;test result
2338 
        trap_ne
2339 
        pla         ;load status
2340 
        eor_flag 0
2341 
        cmp fLDx    ;test flags
2342 
        trap_ne
2343 
        set_stat 0
2344 
        ldy #$82
2345 
        php
2346 
        cpy abs1+1  ;test result
2347 
        trap_ne
2348 
        pla         ;load status
2349 
        eor_flag 0
2350 
        cmp fLDx+1  ;test flags
2351 
        trap_ne
2352 
        set_stat 0
2353 
        ldy #$41
2354 
        php
2355 
        cpy abs1+2  ;test result
2356 
        trap_ne
2357 
        pla         ;load status
2358 
        eor_flag 0
2359 
        cmp fLDx+2  ;test flags
2360 
        trap_ne
2361 
        set_stat 0
2362 
        ldy #0
2363 
        php
2364 
        cpy abs1+3  ;test result
2365 
        trap_ne
2366 
        pla         ;load status
2367 
        eor_flag 0
2368 
        cmp fLDx+3  ;test flags
2369 
        trap_ne
2370 
 
2371 
        set_stat $ff
2372 
        ldy #$c3
2373 
        php
2374 
        cpy abs1    ;test result
2375 
        trap_ne
2376 
        pla         ;load status
2377 
        eor_flag lo~fnz ;mask bits not altered
2378 
        cmp fLDx    ;test flags
2379 
        trap_ne
2380 
        set_stat $ff
2381 
        ldy #$82
2382 
        php
2383 
        cpy abs1+1  ;test result
2384 
        trap_ne
2385 
        pla         ;load status
2386 
        eor_flag lo~fnz ;mask bits not altered
2387 
        cmp fLDx+1  ;test flags
2388 
        trap_ne
2389 
        set_stat $ff
2390 
        ldy #$41
2391 
        php
2392 
        cpy abs1+2   ;test result
2393 
        trap_ne
2394 
        pla         ;load status
2395 
        eor_flag lo~fnz ;mask bits not altered
2396 
        cmp fLDx+2  ;test flags
2397 
        trap_ne
2398 
        set_stat $ff
2399 
        ldy #0
2400 
        php
2401 
        cpy abs1+3  ;test result
2402 
        trap_ne
2403 
        pla         ;load status
2404 
        eor_flag lo~fnz ;mask bits not altered
2405 
        cmp fLDx+3  ;test flags
2406 
        trap_ne
2407 
 
2408 
        ldy #0
2409 
        lda zpt
2410 
        eor #$c3
2411 
        cmp zp1
2412 
        trap_ne     ;store to zp   data
2413 
        sty zpt     ;clear
2414 
        lda abst
2415 
        eor #$c3
2416 
        cmp abs1
2417 
        trap_ne     ;store to abs   data
2418 
        sty abst    ;clear
2419 
        lda zpt+1
2420 
        eor #$c3
2421 
        cmp zp1+1
2422 
        trap_ne     ;store to zp+1 data
2423 
        sty zpt+1   ;clear
2424 
        lda abst+1
2425 
        eor #$c3
2426 
        cmp abs1+1
2427 
        trap_ne     ;store to abs+1 data
2428 
        sty abst+1  ;clear
2429 
        lda zpt+2
2430 
        eor #$c3
2431 
        cmp zp1+2
2432 
        trap_ne     ;store to zp+2 data
2433 
        sty zpt+2   ;clear
2434 
        lda abst+2
2435 
        eor #$c3
2436 
        cmp abs1+2
2437 
        trap_ne     ;store to abs+2 data
2438 
        sty abst+2  ;clear
2439 
        lda zpt+3
2440 
        eor #$c3
2441 
        cmp zp1+3
2442 
        trap_ne     ;store to zp+3 data
2443 
        sty zpt+3   ;clear
2444 
        lda abst+3
2445 
        eor #$c3
2446 
        cmp abs1+3
2447 
        trap_ne     ;store to abs+3 data
2448 
        sty abst+3  ;clear
2449 
 
2450 
; testing load / store accumulator LDA / STA all addressing modes
2451 
; LDA / STA - zp,x / abs,x
2452 
        ldx #3
2453 
tldax
2454 
        set_stat 0
2455 
        lda zp1,x
2456 
        php         ;test stores do not alter flags
2457 
        eor #$c3
2458 
        plp
2459 
        sta abst,x
2460 
        php         ;flags after load/store sequence
2461 
        eor #$c3
2462 
        cmp abs1,x  ;test result
2463 
        trap_ne
2464 
        pla         ;load status
2465 
        eor_flag 0
2466 
        cmp fLDx,x  ;test flags
2467 
        trap_ne
2468 
        dex
2469 
        bpl tldax
2470 
 
2471 
        ldx #3
2472 
tldax1
2473 
        set_stat $ff
2474 
        lda zp1,x
2475 
        php         ;test stores do not alter flags
2476 
        eor #$c3
2477 
        plp
2478 
        sta abst,x
2479 
        php         ;flags after load/store sequence
2480 
        eor #$c3
2481 
        cmp abs1,x   ;test result
2482 
        trap_ne
2483 
        pla         ;load status
2484 
        eor_flag lo~fnz ;mask bits not altered
2485 
        cmp fLDx,x  ;test flags
2486 
        trap_ne
2487 
        dex
2488 
        bpl tldax1
2489 
 
2490 
        ldx #3
2491 
tldax2
2492 
        set_stat 0
2493 
        lda abs1,x
2494 
        php         ;test stores do not alter flags
2495 
        eor #$c3
2496 
        plp
2497 
        sta zpt,x
2498 
        php         ;flags after load/store sequence
2499 
        eor #$c3
2500 
        cmp zp1,x   ;test result
2501 
        trap_ne
2502 
        pla         ;load status
2503 
        eor_flag 0
2504 
        cmp fLDx,x  ;test flags
2505 
        trap_ne
2506 
        dex
2507 
        bpl tldax2
2508 
 
2509 
        ldx #3
2510 
tldax3
2511 
        set_stat $ff
2512 
        lda abs1,x
2513 
        php         ;test stores do not alter flags
2514 
        eor #$c3
2515 
        plp
2516 
        sta zpt,x
2517 
        php         ;flags after load/store sequence
2518 
        eor #$c3
2519 
        cmp zp1,x   ;test result
2520 
        trap_ne
2521 
        pla         ;load status
2522 
        eor_flag lo~fnz ;mask bits not altered
2523 
        cmp fLDx,x  ;test flags
2524 
        trap_ne
2525 
        dex
2526 
        bpl tldax3
2527 
 
2528 
        ldx #3      ;testing store result
2529 
        ldy #0
2530 
tstax   lda zpt,x
2531 
        eor #$c3
2532 
        cmp zp1,x
2533 
        trap_ne     ;store to zp,x data
2534 
        sty zpt,x   ;clear
2535 
        lda abst,x
2536 
        eor #$c3
2537 
        cmp abs1,x
2538 
        trap_ne     ;store to abs,x data
2539 
        txa
2540 
        sta abst,x  ;clear
2541 
        dex
2542 
        bpl tstax
2543 
 
2544 
; LDA / STA - (zp),y / abs,y / (zp,x)
2545 
        ldy #3
2546 
tlday
2547 
        set_stat 0
2548 
        lda (ind1),y
2549 
        php         ;test stores do not alter flags
2550 
        eor #$c3
2551 
        plp
2552 
        sta abst,y
2553 
        php         ;flags after load/store sequence
2554 
        eor #$c3
2555 
        cmp abs1,y  ;test result
2556 
        trap_ne
2557 
        pla         ;load status
2558 
        eor_flag 0
2559 
        cmp fLDx,y  ;test flags
2560 
        trap_ne
2561 
        dey
2562 
        bpl tlday
2563 
 
2564 
        ldy #3
2565 
tlday1
2566 
        set_stat $ff
2567 
        lda (ind1),y
2568 
        php         ;test stores do not alter flags
2569 
        eor #$c3
2570 
        plp
2571 
        sta abst,y
2572 
        php         ;flags after load/store sequence
2573 
        eor #$c3
2574 
        cmp abs1,y  ;test result
2575 
        trap_ne
2576 
        pla         ;load status
2577 
        eor_flag lo~fnz ;mask bits not altered
2578 
        cmp fLDx,y  ;test flags
2579 
        trap_ne
2580 
        dey
2581 
        bpl tlday1
2582 
 
2583 
        ldy #3      ;testing store result
2584 
        ldx #0
2585 
tstay   lda abst,y
2586 
        eor #$c3
2587 
        cmp abs1,y
2588 
        trap_ne     ;store to abs data
2589 
        txa
2590 
        sta abst,y  ;clear
2591 
        dey
2592 
        bpl tstay
2593 
 
2594 
        ldy #3
2595 
tlday2
2596 
        set_stat 0
2597 
        lda abs1,y
2598 
        php         ;test stores do not alter flags
2599 
        eor #$c3
2600 
        plp
2601 
        sta (indt),y
2602 
        php         ;flags after load/store sequence
2603 
        eor #$c3
2604 
        cmp (ind1),y    ;test result
2605 
        trap_ne
2606 
        pla         ;load status
2607 
        eor_flag 0
2608 
        cmp fLDx,y  ;test flags
2609 
        trap_ne
2610 
        dey
2611 
        bpl tlday2
2612 
 
2613 
        ldy #3
2614 
tlday3
2615 
        set_stat $ff
2616 
        lda abs1,y
2617 
        php         ;test stores do not alter flags
2618 
        eor #$c3
2619 
        plp
2620 
        sta (indt),y
2621 
        php         ;flags after load/store sequence
2622 
        eor #$c3
2623 
        cmp (ind1),y   ;test result
2624 
        trap_ne
2625 
        pla         ;load status
2626 
        eor_flag lo~fnz ;mask bits not altered
2627 
        cmp fLDx,y  ;test flags
2628 
        trap_ne
2629 
        dey
2630 
        bpl tlday3
2631 
 
2632 
        ldy #3      ;testing store result
2633 
        ldx #0
2634 
tstay1  lda abst,y
2635 
        eor #$c3
2636 
        cmp abs1,y
2637 
        trap_ne     ;store to abs data
2638 
        txa
2639 
        sta abst,y  ;clear
2640 
        dey
2641 
        bpl tstay1
2642 
 
2643 
        ldx #6
2644 
        ldy #3
2645 
tldax4
2646 
        set_stat 0
2647 
        lda (ind1,x)
2648 
        php         ;test stores do not alter flags
2649 
        eor #$c3
2650 
        plp
2651 
        sta (indt,x)
2652 
        php         ;flags after load/store sequence
2653 
        eor #$c3
2654 
        cmp abs1,y  ;test result
2655 
        trap_ne
2656 
        pla         ;load status
2657 
        eor_flag 0
2658 
        cmp fLDx,y  ;test flags
2659 
        trap_ne
2660 
        dex
2661 
        dex
2662 
        dey
2663 
        bpl tldax4
2664 
 
2665 
        ldx #6
2666 
        ldy #3
2667 
tldax5
2668 
        set_stat $ff
2669 
        lda (ind1,x)
2670 
        php         ;test stores do not alter flags
2671 
        eor #$c3
2672 
        plp
2673 
        sta (indt,x)
2674 
        php         ;flags after load/store sequence
2675 
        eor #$c3
2676 
        cmp abs1,y  ;test result
2677 
        trap_ne
2678 
        pla         ;load status
2679 
        eor_flag lo~fnz ;mask bits not altered
2680 
        cmp fLDx,y  ;test flags
2681 
        trap_ne
2682 
        dex
2683 
        dex
2684 
        dey
2685 
        bpl tldax5
2686 
 
2687 
        ldy #3      ;testing store result
2688 
        ldx #0
2689 
tstay2  lda abst,y
2690 
        eor #$c3
2691 
        cmp abs1,y
2692 
        trap_ne     ;store to abs data
2693 
        txa
2694 
        sta abst,y  ;clear
2695 
        dey
2696 
        bpl tstay2
2697 
 
2698 
; indexed wraparound test (only zp should wrap)
2699 
        ldx #3+$fa
2700 
tldax6  lda zp1-$fa&$ff,x   ;wrap on indexed zp
2701 
        sta abst-$fa,x      ;no STX abs,x!
2702 
        dex
2703 
        cpx #$fa
2704 
        bcs tldax6
2705 
        ldx #3+$fa
2706 
tldax7  lda abs1-$fa,x      ;no wrap on indexed abs
2707 
        sta zpt-$fa&$ff,x
2708 
        dex
2709 
        cpx #$fa
2710 
        bcs tldax7
2711 
 
2712 
        ldx #3      ;testing wraparound result
2713 
        ldy #0
2714 
tstax1  lda zpt,x
2715 
        cmp zp1,x
2716 
        trap_ne     ;store to zp,x data
2717 
        sty zpt,x   ;clear
2718 
        lda abst,x
2719 
        cmp abs1,x
2720 
        trap_ne     ;store to abs,x data
2721 
        txa
2722 
        sta abst,x  ;clear
2723 
        dex
2724 
        bpl tstax1
2725 
 
2726 
        ldy #3+$f8
2727 
        ldx #6+$f8
2728 
tlday4  lda (ind1-$f8&$ff,x) ;wrap on indexed zp indirect
2729 
        sta abst-$f8,y
2730 
        dex
2731 
        dex
2732 
        dey
2733 
        cpy #$f8
2734 
        bcs tlday4
2735 
        ldy #3      ;testing wraparound result
2736 
        ldx #0
2737 
tstay4  lda abst,y
2738 
        cmp abs1,y
2739 
        trap_ne     ;store to abs data
2740 
        txa
2741 
        sta abst,y  ;clear
2742 
        dey
2743 
        bpl tstay4
2744 
 
2745 
        ldy #3+$f8
2746 
tlday5  lda abs1-$f8,y  ;no wrap on indexed abs
2747 
        sta (inwt),y
2748 
        dey
2749 
        cpy #$f8
2750 
        bcs tlday5
2751 
        ldy #3      ;testing wraparound result
2752 
        ldx #0
2753 
tstay5  lda abst,y
2754 
        cmp abs1,y
2755 
        trap_ne     ;store to abs data
2756 
        txa
2757 
        sta abst,y  ;clear
2758 
        dey
2759 
        bpl tstay5
2760 
 
2761 
        ldy #3+$f8
2762 
        ldx #6+$f8
2763 
tlday6  lda (inw1),y    ;no wrap on zp indirect indexed
2764 
        sta (indt-$f8&$ff,x)
2765 
        dex
2766 
        dex
2767 
        dey
2768 
        cpy #$f8
2769 
        bcs tlday6
2770 
        ldy #3      ;testing wraparound result
2771 
        ldx #0
2772 
tstay6  lda abst,y
2773 
        cmp abs1,y
2774 
        trap_ne     ;store to abs data
2775 
        txa
2776 
        sta abst,y  ;clear
2777 
        dey
2778 
        bpl tstay6
2779 
 
2780 
; LDA / STA - zp / abs / #
2781 
        set_stat 0
2782 
        lda zp1
2783 
        php         ;test stores do not alter flags
2784 
        eor #$c3
2785 
        plp
2786 
        sta abst
2787 
        php         ;flags after load/store sequence
2788 
        eor #$c3
2789 
        cmp #$c3    ;test result
2790 
        trap_ne
2791 
        pla         ;load status
2792 
        eor_flag 0
2793 
        cmp fLDx    ;test flags
2794 
        trap_ne
2795 
        set_stat 0
2796 
        lda zp1+1
2797 
        php         ;test stores do not alter flags
2798 
        eor #$c3
2799 
        plp
2800 
        sta abst+1
2801 
        php         ;flags after load/store sequence
2802 
        eor #$c3
2803 
        cmp #$82    ;test result
2804 
        trap_ne
2805 
        pla         ;load status
2806 
        eor_flag 0
2807 
        cmp fLDx+1  ;test flags
2808 
        trap_ne
2809 
        set_stat 0
2810 
        lda zp1+2
2811 
        php         ;test stores do not alter flags
2812 
        eor #$c3
2813 
        plp
2814 
        sta abst+2
2815 
        php         ;flags after load/store sequence
2816 
        eor #$c3
2817 
        cmp #$41    ;test result
2818 
        trap_ne
2819 
        pla         ;load status
2820 
        eor_flag 0
2821 
        cmp fLDx+2  ;test flags
2822 
        trap_ne
2823 
        set_stat 0
2824 
        lda zp1+3
2825 
        php         ;test stores do not alter flags
2826 
        eor #$c3
2827 
        plp
2828 
        sta abst+3
2829 
        php         ;flags after load/store sequence
2830 
        eor #$c3
2831 
        cmp #0      ;test result
2832 
        trap_ne
2833 
        pla         ;load status
2834 
        eor_flag 0
2835 
        cmp fLDx+3  ;test flags
2836 
        trap_ne
2837 
        set_stat $ff
2838 
        lda zp1
2839 
        php         ;test stores do not alter flags
2840 
        eor #$c3
2841 
        plp
2842 
        sta abst
2843 
        php         ;flags after load/store sequence
2844 
        eor #$c3
2845 
        cmp #$c3    ;test result
2846 
        trap_ne
2847 
        pla         ;load status
2848 
        eor_flag lo~fnz ;mask bits not altered
2849 
        cmp fLDx    ;test flags
2850 
        trap_ne
2851 
        set_stat $ff
2852 
        lda zp1+1
2853 
        php         ;test stores do not alter flags
2854 
        eor #$c3
2855 
        plp
2856 
        sta abst+1
2857 
        php         ;flags after load/store sequence
2858 
        eor #$c3
2859 
        cmp #$82    ;test result
2860 
        trap_ne
2861 
        pla         ;load status
2862 
        eor_flag lo~fnz ;mask bits not altered
2863 
        cmp fLDx+1  ;test flags
2864 
        trap_ne
2865 
        set_stat $ff
2866 
        lda zp1+2
2867 
        php         ;test stores do not alter flags
2868 
        eor #$c3
2869 
        plp
2870 
        sta abst+2
2871 
        php         ;flags after load/store sequence
2872 
        eor #$c3
2873 
        cmp #$41    ;test result
2874 
        trap_ne
2875 
        pla         ;load status
2876 
        eor_flag lo~fnz ;mask bits not altered
2877 
        cmp fLDx+2  ;test flags
2878 
        trap_ne
2879 
        set_stat $ff
2880 
        lda zp1+3
2881 
        php         ;test stores do not alter flags
2882 
        eor #$c3
2883 
        plp
2884 
        sta abst+3
2885 
        php         ;flags after load/store sequence
2886 
        eor #$c3
2887 
        cmp #0      ;test result
2888 
        trap_ne
2889 
        pla         ;load status
2890 
        eor_flag lo~fnz ;mask bits not altered
2891 
        cmp fLDx+3  ;test flags
2892 
        trap_ne
2893 
        set_stat 0
2894 
        lda abs1
2895 
        php         ;test stores do not alter flags
2896 
        eor #$c3
2897 
        plp
2898 
        sta zpt
2899 
        php         ;flags after load/store sequence
2900 
        eor #$c3
2901 
        cmp zp1     ;test result
2902 
        trap_ne
2903 
        pla         ;load status
2904 
        eor_flag 0
2905 
        cmp fLDx    ;test flags
2906 
        trap_ne
2907 
        set_stat 0
2908 
        lda abs1+1
2909 
        php         ;test stores do not alter flags
2910 
        eor #$c3
2911 
        plp
2912 
        sta zpt+1
2913 
        php         ;flags after load/store sequence
2914 
        eor #$c3
2915 
        cmp zp1+1   ;test result
2916 
        trap_ne
2917 
        pla         ;load status
2918 
        eor_flag 0
2919 
        cmp fLDx+1  ;test flags
2920 
        trap_ne
2921 
        set_stat 0
2922 
        lda abs1+2
2923 
        php         ;test stores do not alter flags
2924 
        eor #$c3
2925 
        plp
2926 
        sta zpt+2
2927 
        php         ;flags after load/store sequence
2928 
        eor #$c3
2929 
        cmp zp1+2   ;test result
2930 
        trap_ne
2931 
        pla         ;load status
2932 
        eor_flag 0
2933 
        cmp fLDx+2  ;test flags
2934 
        trap_ne
2935 
        set_stat 0
2936 
        lda abs1+3
2937 
        php         ;test stores do not alter flags
2938 
        eor #$c3
2939 
        plp
2940 
        sta zpt+3
2941 
        php         ;flags after load/store sequence
2942 
        eor #$c3
2943 
        cmp zp1+3   ;test result
2944 
        trap_ne
2945 
        pla         ;load status
2946 
        eor_flag 0
2947 
        cmp fLDx+3  ;test flags
2948 
        trap_ne
2949 
        set_stat $ff
2950 
        lda abs1
2951 
        php         ;test stores do not alter flags
2952 
        eor #$c3
2953 
        plp
2954 
        sta zpt
2955 
        php         ;flags after load/store sequence
2956 
        eor #$c3
2957 
        cmp zp1     ;test result
2958 
        trap_ne
2959 
        pla         ;load status
2960 
        eor_flag lo~fnz ;mask bits not altered
2961 
        cmp fLDx    ;test flags
2962 
        trap_ne
2963 
        set_stat $ff
2964 
        lda abs1+1
2965 
        php         ;test stores do not alter flags
2966 
        eor #$c3
2967 
        plp
2968 
        sta zpt+1
2969 
        php         ;flags after load/store sequence
2970 
        eor #$c3
2971 
        cmp zp1+1   ;test result
2972 
        trap_ne
2973 
        pla         ;load status
2974 
        eor_flag lo~fnz ;mask bits not altered
2975 
        cmp fLDx+1  ;test flags
2976 
        trap_ne
2977 
        set_stat $ff
2978 
        lda abs1+2
2979 
        php         ;test stores do not alter flags
2980 
        eor #$c3
2981 
        plp
2982 
        sta zpt+2
2983 
        php         ;flags after load/store sequence
2984 
        eor #$c3
2985 
        cmp zp1+2   ;test result
2986 
        trap_ne
2987 
        pla         ;load status
2988 
        eor_flag lo~fnz ;mask bits not altered
2989 
        cmp fLDx+2  ;test flags
2990 
        trap_ne
2991 
        set_stat $ff
2992 
        lda abs1+3
2993 
        php         ;test stores do not alter flags
2994 
        eor #$c3
2995 
        plp
2996 
        sta zpt+3
2997 
        php         ;flags after load/store sequence
2998 
        eor #$c3
2999 
        cmp zp1+3   ;test result
3000 
        trap_ne
3001 
        pla         ;load status
3002 
        eor_flag lo~fnz ;mask bits not altered
3003 
        cmp fLDx+3  ;test flags
3004 
        trap_ne
3005 
        set_stat 0
3006 
        lda #$c3
3007 
        php
3008 
        cmp abs1    ;test result
3009 
        trap_ne
3010 
        pla         ;load status
3011 
        eor_flag 0
3012 
        cmp fLDx    ;test flags
3013 
        trap_ne
3014 
        set_stat 0
3015 
        lda #$82
3016 
        php
3017 
        cmp abs1+1  ;test result
3018 
        trap_ne
3019 
        pla         ;load status
3020 
        eor_flag 0
3021 
        cmp fLDx+1  ;test flags
3022 
        trap_ne
3023 
        set_stat 0
3024 
        lda #$41
3025 
        php
3026 
        cmp abs1+2  ;test result
3027 
        trap_ne
3028 
        pla         ;load status
3029 
        eor_flag 0
3030 
        cmp fLDx+2  ;test flags
3031 
        trap_ne
3032 
        set_stat 0
3033 
        lda #0
3034 
        php
3035 
        cmp abs1+3  ;test result
3036 
        trap_ne
3037 
        pla         ;load status
3038 
        eor_flag 0
3039 
        cmp fLDx+3  ;test flags
3040 
        trap_ne
3041 
 
3042 
        set_stat $ff
3043 
        lda #$c3
3044 
        php
3045 
        cmp abs1    ;test result
3046 
        trap_ne
3047 
        pla         ;load status
3048 
        eor_flag lo~fnz ;mask bits not altered
3049 
        cmp fLDx    ;test flags
3050 
        trap_ne
3051 
        set_stat $ff
3052 
        lda #$82
3053 
        php
3054 
        cmp abs1+1  ;test result
3055 
        trap_ne
3056 
        pla         ;load status
3057 
        eor_flag lo~fnz ;mask bits not altered
3058 
        cmp fLDx+1  ;test flags
3059 
        trap_ne
3060 
        set_stat $ff
3061 
        lda #$41
3062 
        php
3063 
        cmp abs1+2  ;test result
3064 
        trap_ne
3065 
        pla         ;load status
3066 
        eor_flag lo~fnz ;mask bits not altered
3067 
        cmp fLDx+2  ;test flags
3068 
        trap_ne
3069 
        set_stat $ff
3070 
        lda #0
3071 
        php
3072 
        cmp abs1+3  ;test result
3073 
        trap_ne
3074 
        pla         ;load status
3075 
        eor_flag lo~fnz ;mask bits not altered
3076 
        cmp fLDx+3  ;test flags
3077 
        trap_ne
3078 
 
3079 
        ldx #0
3080 
        lda zpt
3081 
        eor #$c3
3082 
        cmp zp1
3083 
        trap_ne     ;store to zp data
3084 
        stx zpt     ;clear
3085 
        lda abst
3086 
        eor #$c3
3087 
        cmp abs1
3088 
        trap_ne     ;store to abs data
3089 
        stx abst    ;clear
3090 
        lda zpt+1
3091 
        eor #$c3
3092 
        cmp zp1+1
3093 
        trap_ne     ;store to zp data
3094 
        stx zpt+1   ;clear
3095 
        lda abst+1
3096 
        eor #$c3
3097 
        cmp abs1+1
3098 
        trap_ne     ;store to abs data
3099 
        stx abst+1  ;clear
3100 
        lda zpt+2
3101 
        eor #$c3
3102 
        cmp zp1+2
3103 
        trap_ne     ;store to zp data
3104 
        stx zpt+2   ;clear
3105 
        lda abst+2
3106 
        eor #$c3
3107 
        cmp abs1+2
3108 
        trap_ne     ;store to abs data
3109 
        stx abst+2  ;clear
3110 
        lda zpt+3
3111 
        eor #$c3
3112 
        cmp zp1+3
3113 
        trap_ne     ;store to zp data
3114 
        stx zpt+3   ;clear
3115 
        lda abst+3
3116 
        eor #$c3
3117 
        cmp abs1+3
3118 
        trap_ne     ;store to abs data
3119 
        stx abst+3  ;clear
3120 
 
3121 
; testing bit test & compares BIT CPX CPY CMP all addressing modes
3122 
; BIT - zp / abs
3123 
        set_a $ff,0
3124 
        bit zp1+3   ;00 - should set Z / clear  NV
3125 
        tst_a $ff,fz
3126 
        set_a 1,0
3127 
        bit zp1+2   ;41 - should set V (M6) / clear NZ
3128 
        tst_a 1,fv
3129 
        set_a 1,0
3130 
        bit zp1+1   ;82 - should set N (M7) & Z / clear V
3131 
        tst_a 1,fnz
3132 
        set_a 1,0
3133 
        bit zp1     ;c3 - should set N (M7) & V (M6) / clear Z
3134 
        tst_a 1,fnv
3135 
 
3136 
        set_a $ff,$ff
3137 
        bit zp1+3   ;00 - should set Z / clear  NV
3138 
        tst_a $ff,~fnv
3139 
        set_a 1,$ff
3140 
        bit zp1+2   ;41 - should set V (M6) / clear NZ
3141 
        tst_a 1,~fnz
3142 
        set_a 1,$ff
3143 
        bit zp1+1   ;82 - should set N (M7) & Z / clear V
3144 
        tst_a 1,~fv
3145 
        set_a 1,$ff
3146 
        bit zp1     ;c3 - should set N (M7) & V (M6) / clear Z
3147 
        tst_a 1,~fz
3148 
 
3149 
        set_a $ff,0
3150 
        bit abs1+3  ;00 - should set Z / clear  NV
3151 
        tst_a $ff,fz
3152 
        set_a 1,0
3153 
        bit abs1+2  ;41 - should set V (M6) / clear NZ
3154 
        tst_a 1,fv
3155 
        set_a 1,0
3156 
        bit abs1+1  ;82 - should set N (M7) & Z / clear V
3157 
        tst_a 1,fnz
3158 
        set_a 1,0
3159 
        bit abs1    ;c3 - should set N (M7) & V (M6) / clear Z
3160 
        tst_a 1,fnv
3161 
 
3162 
        set_a $ff,$ff
3163 
        bit abs1+3  ;00 - should set Z / clear  NV
3164 
        tst_a $ff,~fnv
3165 
        set_a 1,$ff
3166 
        bit abs1+2  ;41 - should set V (M6) / clear NZ
3167 
        tst_a 1,~fnz
3168 
        set_a 1,$ff
3169 
        bit abs1+1  ;82 - should set N (M7) & Z / clear V
3170 
        tst_a 1,~fv
3171 
        set_a 1,$ff
3172 
        bit abs1    ;c3 - should set N (M7) & V (M6) / clear Z
3173 
        tst_a 1,~fz
3174 
 
3175 
; CPX - zp / abs / #
3176 
        set_x $80,0
3177 
        cpx zp7f
3178 
        tst_stat fc
3179 
        dex
3180 
        cpx zp7f
3181 
        tst_stat fzc
3182 
        dex
3183 
        cpx zp7f
3184 
        tst_x $7e,fn
3185 
        set_x $80,$ff
3186 
        cpx zp7f
3187 
        tst_stat ~fnz
3188 
        dex
3189 
        cpx zp7f
3190 
        tst_stat ~fn
3191 
        dex
3192 
        cpx zp7f
3193 
        tst_x $7e,~fzc
3194 
 
3195 
        set_x $80,0
3196 
        cpx abs7f
3197 
        tst_stat fc
3198 
        dex
3199 
        cpx abs7f
3200 
        tst_stat fzc
3201 
        dex
3202 
        cpx abs7f
3203 
        tst_x $7e,fn
3204 
        set_x $80,$ff
3205 
        cpx abs7f
3206 
        tst_stat ~fnz
3207 
        dex
3208 
        cpx abs7f
3209 
        tst_stat ~fn
3210 
        dex
3211 
        cpx abs7f
3212 
        tst_x $7e,~fzc
3213 
 
3214 
        set_x $80,0
3215 
        cpx #$7f
3216 
        tst_stat fc
3217 
        dex
3218 
        cpx #$7f
3219 
        tst_stat fzc
3220 
        dex
3221 
        cpx #$7f
3222 
        tst_x $7e,fn
3223 
        set_x $80,$ff
3224 
        cpx #$7f
3225 
        tst_stat ~fnz
3226 
        dex
3227 
        cpx #$7f
3228 
        tst_stat ~fn
3229 
        dex
3230 
        cpx #$7f
3231 
        tst_x $7e,~fzc
3232 
 
3233 
; CPY - zp / abs / #
3234 
        set_y $80,0
3235 
        cpy zp7f
3236 
        tst_stat fc
3237 
        dey
3238 
        cpy zp7f
3239 
        tst_stat fzc
3240 
        dey
3241 
        cpy zp7f
3242 
        tst_y $7e,fn
3243 
        set_y $80,$ff
3244 
        cpy zp7f
3245 
        tst_stat ~fnz
3246 
        dey
3247 
        cpy zp7f
3248 
        tst_stat ~fn
3249 
        dey
3250 
        cpy zp7f
3251 
        tst_y $7e,~fzc
3252 
 
3253 
        set_y $80,0
3254 
        cpy abs7f
3255 
        tst_stat fc
3256 
        dey
3257 
        cpy abs7f
3258 
        tst_stat fzc
3259 
        dey
3260 
        cpy abs7f
3261 
        tst_y $7e,fn
3262 
        set_y $80,$ff
3263 
        cpy abs7f
3264 
        tst_stat ~fnz
3265 
        dey
3266 
        cpy abs7f
3267 
        tst_stat ~fn
3268 
        dey
3269 
        cpy abs7f
3270 
        tst_y $7e,~fzc
3271 
 
3272 
        set_y $80,0
3273 
        cpy #$7f
3274 
        tst_stat fc
3275 
        dey
3276 
        cpy #$7f
3277 
        tst_stat fzc
3278 
        dey
3279 
        cpy #$7f
3280 
        tst_y $7e,fn
3281 
        set_y $80,$ff
3282 
        cpy #$7f
3283 
        tst_stat ~fnz
3284 
        dey
3285 
        cpy #$7f
3286 
        tst_stat ~fn
3287 
        dey
3288 
        cpy #$7f
3289 
        tst_y $7e,~fzc
3290 
 
3291 
; CMP - zp / abs / #
3292 
        set_a $80,0
3293 
        cmp zp7f
3294 
        tst_a $80,fc
3295 
        set_a $7f,0
3296 
        cmp zp7f
3297 
        tst_a $7f,fzc
3298 
        set_a $7e,0
3299 
        cmp zp7f
3300 
        tst_a $7e,fn
3301 
        set_a $80,$ff
3302 
        cmp zp7f
3303 
        tst_a $80,~fnz
3304 
        set_a $7f,$ff
3305 
        cmp zp7f
3306 
        tst_a $7f,~fn
3307 
        set_a $7e,$ff
3308 
        cmp zp7f
3309 
        tst_a $7e,~fzc
3310 
 
3311 
        set_a $80,0
3312 
        cmp abs7f
3313 
        tst_a $80,fc
3314 
        set_a $7f,0
3315 
        cmp abs7f
3316 
        tst_a $7f,fzc
3317 
        set_a $7e,0
3318 
        cmp abs7f
3319 
        tst_a $7e,fn
3320 
        set_a $80,$ff
3321 
        cmp abs7f
3322 
        tst_a $80,~fnz
3323 
        set_a $7f,$ff
3324 
        cmp abs7f
3325 
        tst_a $7f,~fn
3326 
        set_a $7e,$ff
3327 
        cmp abs7f
3328 
        tst_a $7e,~fzc
3329 
 
3330 
        set_a $80,0
3331 
        cmp #$7f
3332 
        tst_a $80,fc
3333 
        set_a $7f,0
3334 
        cmp #$7f
3335 
        tst_a $7f,fzc
3336 
        set_a $7e,0
3337 
        cmp #$7f
3338 
        tst_a $7e,fn
3339 
        set_a $80,$ff
3340 
        cmp #$7f
3341 
        tst_a $80,~fnz
3342 
        set_a $7f,$ff
3343 
        cmp #$7f
3344 
        tst_a $7f,~fn
3345 
        set_a $7e,$ff
3346 
        cmp #$7f
3347 
        tst_a $7e,~fzc
3348 
 
3349 
        ldx #4          ;with indexing by X
3350 
        set_a $80,0
3351 
        cmp zp1,x
3352 
        tst_a $80,fc
3353 
        set_a $7f,0
3354 
        cmp zp1,x
3355 
        tst_a $7f,fzc
3356 
        set_a $7e,0
3357 
        cmp zp1,x
3358 
        tst_a $7e,fn
3359 
        set_a $80,$ff
3360 
        cmp zp1,x
3361 
        tst_a $80,~fnz
3362 
        set_a $7f,$ff
3363 
        cmp zp1,x
3364 
        tst_a $7f,~fn
3365 
        set_a $7e,$ff
3366 
        cmp zp1,x
3367 
        tst_a $7e,~fzc
3368 
 
3369 
        set_a $80,0
3370 
        cmp abs1,x
3371 
        tst_a $80,fc
3372 
        set_a $7f,0
3373 
        cmp abs1,x
3374 
        tst_a $7f,fzc
3375 
        set_a $7e,0
3376 
        cmp abs1,x
3377 
        tst_a $7e,fn
3378 
        set_a $80,$ff
3379 
        cmp abs1,x
3380 
        tst_a $80,~fnz
3381 
        set_a $7f,$ff
3382 
        cmp abs1,x
3383 
        tst_a $7f,~fn
3384 
        set_a $7e,$ff
3385 
        cmp abs1,x
3386 
        tst_a $7e,~fzc
3387 
 
3388 
        ldy #4          ;with indexing by Y
3389 
        ldx #8          ;with indexed indirect
3390 
        set_a $80,0
3391 
        cmp abs1,y
3392 
        tst_a $80,fc
3393 
        set_a $7f,0
3394 
        cmp abs1,y
3395 
        tst_a $7f,fzc
3396 
        set_a $7e,0
3397 
        cmp abs1,y
3398 
        tst_a $7e,fn
3399 
        set_a $80,$ff
3400 
        cmp abs1,y
3401 
        tst_a $80,~fnz
3402 
        set_a $7f,$ff
3403 
        cmp abs1,y
3404 
        tst_a $7f,~fn
3405 
        set_a $7e,$ff
3406 
        cmp abs1,y
3407 
        tst_a $7e,~fzc
3408 
 
3409 
        set_a $80,0
3410 
        cmp (ind1,x)
3411 
        tst_a $80,fc
3412 
        set_a $7f,0
3413 
        cmp (ind1,x)
3414 
        tst_a $7f,fzc
3415 
        set_a $7e,0
3416 
        cmp (ind1,x)
3417 
        tst_a $7e,fn
3418 
        set_a $80,$ff
3419 
        cmp (ind1,x)
3420 
        tst_a $80,~fnz
3421 
        set_a $7f,$ff
3422 
        cmp (ind1,x)
3423 
        tst_a $7f,~fn
3424 
        set_a $7e,$ff
3425 
        cmp (ind1,x)
3426 
        tst_a $7e,~fzc
3427 
 
3428 
        set_a $80,0
3429 
        cmp (ind1),y
3430 
        tst_a $80,fc
3431 
        set_a $7f,0
3432 
        cmp (ind1),y
3433 
        tst_a $7f,fzc
3434 
        set_a $7e,0
3435 
        cmp (ind1),y
3436 
        tst_a $7e,fn
3437 
        set_a $80,$ff
3438 
        cmp (ind1),y
3439 
        tst_a $80,~fnz
3440 
        set_a $7f,$ff
3441 
        cmp (ind1),y
3442 
        tst_a $7f,~fn
3443 
        set_a $7e,$ff
3444 
        cmp (ind1),y
3445 
        tst_a $7e,~fzc
3446 
 
3447 
; testing shifts - ASL LSR ROL ROR all addressing modes
3448 
; shifts - accumulator
3449 
        ldx #3
3450 
tasl
3451 
        set_ax zp1,0
3452 
        asl a
3453 
        tst_ax rASL,fASL,0
3454 
        dex
3455 
        bpl tasl
3456 
        ldx #3
3457 
tasl1
3458 
        set_ax zp1,$ff
3459 
        asl a
3460 
        tst_ax rASL,fASL,$ff-fnzc
3461 
        dex
3462 
        bpl tasl1
3463 
 
3464 
        ldx #3
3465 
tlsr
3466 
        set_ax zp1,0
3467 
        lsr a
3468 
        tst_ax rLSR,fLSR,0
3469 
        dex
3470 
        bpl tlsr
3471 
        ldx #3
3472 
tlsr1
3473 
        set_ax zp1,$ff
3474 
        lsr a
3475 
        tst_ax rLSR,fLSR,$ff-fnzc
3476 
        dex
3477 
        bpl tlsr1
3478 
 
3479 
        ldx #3
3480 
trol
3481 
        set_ax zp1,0
3482 
        rol a
3483 
        tst_ax rROL,fROL,0
3484 
        dex
3485 
        bpl trol
3486 
        ldx #3
3487 
trol1
3488 
        set_ax zp1,$ff-fc
3489 
        rol a
3490 
        tst_ax rROL,fROL,$ff-fnzc
3491 
        dex
3492 
        bpl trol1
3493 
 
3494 
        ldx #3
3495 
trolc
3496 
        set_ax zp1,fc
3497 
        rol a
3498 
        tst_ax rROLc,fROLc,0
3499 
        dex
3500 
        bpl trolc
3501 
        ldx #3
3502 
trolc1
3503 
        set_ax zp1,$ff
3504 
        rol a
3505 
        tst_ax rROLc,fROLc,$ff-fnzc
3506 
        dex
3507 
        bpl trolc1
3508 
 
3509 
        ldx #3
3510 
tror
3511 
        set_ax zp1,0
3512 
        ror a
3513 
        tst_ax rROR,fROR,0
3514 
        dex
3515 
        bpl tror
3516 
        ldx #3
3517 
tror1
3518 
        set_ax zp1,$ff-fc
3519 
        ror a
3520 
        tst_ax rROR,fROR,$ff-fnzc
3521 
        dex
3522 
        bpl tror1
3523 
 
3524 
        ldx #3
3525 
trorc
3526 
        set_ax zp1,fc
3527 
        ror a
3528 
        tst_ax rRORc,fRORc,0
3529 
        dex
3530 
        bpl trorc
3531 
        ldx #3
3532 
trorc1
3533 
        set_ax zp1,$ff
3534 
        ror a
3535 
        tst_ax rRORc,fRORc,$ff-fnzc
3536 
        dex
3537 
        bpl trorc1
3538 
 
3539 
; shifts - zeropage
3540 
        ldx #3
3541 
tasl2
3542 
        set_z zp1,0
3543 
        asl zpt
3544 
        tst_z rASL,fASL,0
3545 
        dex
3546 
        bpl tasl2
3547 
        ldx #3
3548 
tasl3
3549 
        set_z zp1,$ff
3550 
        asl zpt
3551 
        tst_z rASL,fASL,$ff-fnzc
3552 
        dex
3553 
        bpl tasl3
3554 
 
3555 
        ldx #3
3556 
tlsr2
3557 
        set_z zp1,0
3558 
        lsr zpt
3559 
        tst_z rLSR,fLSR,0
3560 
        dex
3561 
        bpl tlsr2
3562 
        ldx #3
3563 
tlsr3
3564 
        set_z zp1,$ff
3565 
        lsr zpt
3566 
        tst_z rLSR,fLSR,$ff-fnzc
3567 
        dex
3568 
        bpl tlsr3
3569 
 
3570 
        ldx #3
3571 
trol2
3572 
        set_z zp1,0
3573 
        rol zpt
3574 
        tst_z rROL,fROL,0
3575 
        dex
3576 
        bpl trol2
3577 
        ldx #3
3578 
trol3
3579 
        set_z zp1,$ff-fc
3580 
        rol zpt
3581 
        tst_z rROL,fROL,$ff-fnzc
3582 
        dex
3583 
        bpl trol3
3584 
 
3585 
        ldx #3
3586 
trolc2
3587 
        set_z zp1,fc
3588 
        rol zpt
3589 
        tst_z rROLc,fROLc,0
3590 
        dex
3591 
        bpl trolc2
3592 
        ldx #3
3593 
trolc3
3594 
        set_z zp1,$ff
3595 
        rol zpt
3596 
        tst_z rROLc,fROLc,$ff-fnzc
3597 
        dex
3598 
        bpl trolc3
3599 
 
3600 
        ldx #3
3601 
tror2
3602 
        set_z zp1,0
3603 
        ror zpt
3604 
        tst_z rROR,fROR,0
3605 
        dex
3606 
        bpl tror2
3607 
        ldx #3
3608 
tror3
3609 
        set_z zp1,$ff-fc
3610 
        ror zpt
3611 
        tst_z rROR,fROR,$ff-fnzc
3612 
        dex
3613 
        bpl tror3
3614 
 
3615 
        ldx #3
3616 
trorc2
3617 
        set_z zp1,fc
3618 
        ror zpt
3619 
        tst_z rRORc,fRORc,0
3620 
        dex
3621 
        bpl trorc2
3622 
        ldx #3
3623 
trorc3
3624 
        set_z zp1,$ff
3625 
        ror zpt
3626 
        tst_z rRORc,fRORc,$ff-fnzc
3627 
        dex
3628 
        bpl trorc3
3629 
 
3630 
; shifts - absolute
3631 
        ldx #3
3632 
tasl4
3633 
        set_abs zp1,0
3634 
        asl abst
3635 
        tst_abs rASL,fASL,0
3636 
        dex
3637 
        bpl tasl4
3638 
        ldx #3
3639 
tasl5
3640 
        set_abs zp1,$ff
3641 
        asl abst
3642 
        tst_abs rASL,fASL,$ff-fnzc
3643 
        dex
3644 
        bpl tasl5
3645 
 
3646 
        ldx #3
3647 
tlsr4
3648 
        set_abs zp1,0
3649 
        lsr abst
3650 
        tst_abs rLSR,fLSR,0
3651 
        dex
3652 
        bpl tlsr4
3653 
        ldx #3
3654 
tlsr5
3655 
        set_abs zp1,$ff
3656 
        lsr abst
3657 
        tst_abs rLSR,fLSR,$ff-fnzc
3658 
        dex
3659 
        bpl tlsr5
3660 
 
3661 
        ldx #3
3662 
trol4
3663 
        set_abs zp1,0
3664 
        rol abst
3665 
        tst_abs rROL,fROL,0
3666 
        dex
3667 
        bpl trol4
3668 
        ldx #3
3669 
trol5
3670 
        set_abs zp1,$ff-fc
3671 
        rol abst
3672 
        tst_abs rROL,fROL,$ff-fnzc
3673 
        dex
3674 
        bpl trol5
3675 
 
3676 
        ldx #3
3677 
trolc4
3678 
        set_abs zp1,fc
3679 
        rol abst
3680 
        tst_abs rROLc,fROLc,0
3681 
        dex
3682 
        bpl trolc4
3683 
        ldx #3
3684 
trolc5
3685 
        set_abs zp1,$ff
3686 
        rol abst
3687 
        tst_abs rROLc,fROLc,$ff-fnzc
3688 
        dex
3689 
        bpl trolc5
3690 
 
3691 
        ldx #3
3692 
tror4
3693 
        set_abs zp1,0
3694 
        ror abst
3695 
        tst_abs rROR,fROR,0
3696 
        dex
3697 
        bpl tror4
3698 
        ldx #3
3699 
tror5
3700 
        set_abs zp1,$ff-fc
3701 
        ror abst
3702 
        tst_abs rROR,fROR,$ff-fnzc
3703 
        dex
3704 
        bpl tror5
3705 
 
3706 
        ldx #3
3707 
trorc4
3708 
        set_abs zp1,fc
3709 
        ror abst
3710 
        tst_abs rRORc,fRORc,0
3711 
        dex
3712 
        bpl trorc4
3713 
        ldx #3
3714 
trorc5
3715 
        set_abs zp1,$ff
3716 
        ror abst
3717 
        tst_abs rRORc,fRORc,$ff-fnzc
3718 
        dex
3719 
        bpl trorc5
3720 
 
3721 
; shifts - zp indexed
3722 
        ldx #3
3723 
tasl6
3724 
        set_zx zp1,0
3725 
        asl zpt,x
3726 
        tst_zx rASL,fASL,0
3727 
        dex
3728 
        bpl tasl6
3729 
        ldx #3
3730 
tasl7
3731 
        set_zx zp1,$ff
3732 
        asl zpt,x
3733 
        tst_zx rASL,fASL,$ff-fnzc
3734 
        dex
3735 
        bpl tasl7
3736 
 
3737 
        ldx #3
3738 
tlsr6
3739 
        set_zx zp1,0
3740 
        lsr zpt,x
3741 
        tst_zx rLSR,fLSR,0
3742 
        dex
3743 
        bpl tlsr6
3744 
        ldx #3
3745 
tlsr7
3746 
        set_zx zp1,$ff
3747 
        lsr zpt,x
3748 
        tst_zx rLSR,fLSR,$ff-fnzc
3749 
        dex
3750 
        bpl tlsr7
3751 
 
3752 
        ldx #3
3753 
trol6
3754 
        set_zx zp1,0
3755 
        rol zpt,x
3756 
        tst_zx rROL,fROL,0
3757 
        dex
3758 
        bpl trol6
3759 
        ldx #3
3760 
trol7
3761 
        set_zx zp1,$ff-fc
3762 
        rol zpt,x
3763 
        tst_zx rROL,fROL,$ff-fnzc
3764 
        dex
3765 
        bpl trol7
3766 
 
3767 
        ldx #3
3768 
trolc6
3769 
        set_zx zp1,fc
3770 
        rol zpt,x
3771 
        tst_zx rROLc,fROLc,0
3772 
        dex
3773 
        bpl trolc6
3774 
        ldx #3
3775 
trolc7
3776 
        set_zx zp1,$ff
3777 
        rol zpt,x
3778 
        tst_zx rROLc,fROLc,$ff-fnzc
3779 
        dex
3780 
        bpl trolc7
3781 
 
3782 
        ldx #3
3783 
tror6
3784 
        set_zx zp1,0
3785 
        ror zpt,x
3786 
        tst_zx rROR,fROR,0
3787 
        dex
3788 
        bpl tror6
3789 
        ldx #3
3790 
tror7
3791 
        set_zx zp1,$ff-fc
3792 
        ror zpt,x
3793 
        tst_zx rROR,fROR,$ff-fnzc
3794 
        dex
3795 
        bpl tror7
3796 
 
3797 
        ldx #3
3798 
trorc6
3799 
        set_zx zp1,fc
3800 
        ror zpt,x
3801 
        tst_zx rRORc,fRORc,0
3802 
        dex
3803 
        bpl trorc6
3804 
        ldx #3
3805 
trorc7
3806 
        set_zx zp1,$ff
3807 
        ror zpt,x
3808 
        tst_zx rRORc,fRORc,$ff-fnzc
3809 
        dex
3810 
        bpl trorc7
3811 
 
3812 
; shifts - abs indexed
3813 
        ldx #3
3814 
tasl8
3815 
        set_absx zp1,0
3816 
        asl abst,x
3817 
        tst_absx rASL,fASL,0
3818 
        dex
3819 
        bpl tasl8
3820 
        ldx #3
3821 
tasl9
3822 
        set_absx zp1,$ff
3823 
        asl abst,x
3824 
        tst_absx rASL,fASL,$ff-fnzc
3825 
        dex
3826 
        bpl tasl9
3827 
 
3828 
        ldx #3
3829 
tlsr8
3830 
        set_absx zp1,0
3831 
        lsr abst,x
3832 
        tst_absx rLSR,fLSR,0
3833 
        dex
3834 
        bpl tlsr8
3835 
        ldx #3
3836 
tlsr9
3837 
        set_absx zp1,$ff
3838 
        lsr abst,x
3839 
        tst_absx rLSR,fLSR,$ff-fnzc
3840 
        dex
3841 
        bpl tlsr9
3842 
 
3843 
        ldx #3
3844 
trol8
3845 
        set_absx zp1,0
3846 
        rol abst,x
3847 
        tst_absx rROL,fROL,0
3848 
        dex
3849 
        bpl trol8
3850 
        ldx #3
3851 
trol9
3852 
        set_absx zp1,$ff-fc
3853 
        rol abst,x
3854 
        tst_absx rROL,fROL,$ff-fnzc
3855 
        dex
3856 
        bpl trol9
3857 
 
3858 
        ldx #3
3859 
trolc8
3860 
        set_absx zp1,fc
3861 
        rol abst,x
3862 
        tst_absx rROLc,fROLc,0
3863 
        dex
3864 
        bpl trolc8
3865 
        ldx #3
3866 
trolc9
3867 
        set_absx zp1,$ff
3868 
        rol abst,x
3869 
        tst_absx rROLc,fROLc,$ff-fnzc
3870 
        dex
3871 
        bpl trolc9
3872 
 
3873 
        ldx #3
3874 
tror8
3875 
        set_absx zp1,0
3876 
        ror abst,x
3877 
        tst_absx rROR,fROR,0
3878 
        dex
3879 
        bpl tror8
3880 
        ldx #3
3881 
tror9
3882 
        set_absx zp1,$ff-fc
3883 
        ror abst,x
3884 
        tst_absx rROR,fROR,$ff-fnzc
3885 
        dex
3886 
        bpl tror9
3887 
 
3888 
        ldx #3
3889 
trorc8
3890 
        set_absx zp1,fc
3891 
        ror abst,x
3892 
        tst_absx rRORc,fRORc,0
3893 
        dex
3894 
        bpl trorc8
3895 
        ldx #3
3896 
trorc9
3897 
        set_absx zp1,$ff
3898 
        ror abst,x
3899 
        tst_absx rRORc,fRORc,$ff-fnzc
3900 
        dex
3901 
        bpl trorc9
3902 
 
3903 
; testing memory increment/decrement - INC DEC all addressing modes
3904 
; zeropage
3905 
        ldx #0
3906 
        lda #$7e
3907 
        sta zpt
3908 
tinc
3909 
        set_stat 0
3910 
        inc zpt
3911 
        tst_z rINC,fINC,0
3912 
        inx
3913 
        cpx #2
3914 
        bne tinc1
3915 
        lda #$fe
3916 
        sta zpt
3917 
tinc1   cpx #5
3918 
        bne tinc
3919 
        dex
3920 
        inc zpt
3921 
tdec
3922 
        set_stat 0
3923 
        dec zpt
3924 
        tst_z rINC,fINC,0
3925 
        dex
3926 
        bmi tdec1
3927 
        cpx #1
3928 
        bne tdec
3929 
        lda #$81
3930 
        sta zpt
3931 
        bne tdec
3932 
tdec1
3933 
        ldx #0
3934 
        lda #$7e
3935 
        sta zpt
3936 
tinc10
3937 
        set_stat $ff
3938 
        inc zpt
3939 
        tst_z rINC,fINC,$ff-fnz
3940 
        inx
3941 
        cpx #2
3942 
        bne tinc11
3943 
        lda #$fe
3944 
        sta zpt
3945 
tinc11  cpx #5
3946 
        bne tinc10
3947 
        dex
3948 
        inc zpt
3949 
tdec10
3950 
        set_stat $ff
3951 
        dec zpt
3952 
        tst_z rINC,fINC,$ff-fnz
3953 
        dex
3954 
        bmi tdec11
3955 
        cpx #1
3956 
        bne tdec10
3957 
        lda #$81
3958 
        sta zpt
3959 
        bne tdec10
3960 
tdec11
3961 
 
3962 
; absolute memory
3963 
        ldx #0
3964 
        lda #$7e
3965 
        sta abst
3966 
tinc2
3967 
        set_stat 0
3968 
        inc abst
3969 
        tst_abs rINC,fINC,0
3970 
        inx
3971 
        cpx #2
3972 
        bne tinc3
3973 
        lda #$fe
3974 
        sta abst
3975 
tinc3   cpx #5
3976 
        bne tinc2
3977 
        dex
3978 
        inc abst
3979 
tdec2
3980 
        set_stat 0
3981 
        dec abst
3982 
        tst_abs rINC,fINC,0
3983 
        dex
3984 
        bmi tdec3
3985 
        cpx #1
3986 
        bne tdec2
3987 
        lda #$81
3988 
        sta abst
3989 
        bne tdec2
3990 
tdec3
3991 
        ldx #0
3992 
        lda #$7e
3993 
        sta abst
3994 
tinc12
3995 
        set_stat $ff
3996 
        inc abst
3997 
        tst_abs rINC,fINC,$ff-fnz
3998 
        inx
3999 
        cpx #2
4000 
        bne tinc13
4001 
        lda #$fe
4002 
        sta abst
4003 
tinc13   cpx #5
4004 
        bne tinc12
4005 
        dex
4006 
        inc abst
4007 
tdec12
4008 
        set_stat $ff
4009 
        dec abst
4010 
        tst_abs rINC,fINC,$ff-fnz
4011 
        dex
4012 
        bmi tdec13
4013 
        cpx #1
4014 
        bne tdec12
4015 
        lda #$81
4016 
        sta abst
4017 
        bne tdec12
4018 
tdec13
4019 
 
4020 
; zeropage indexed
4021 
        ldx #0
4022 
        lda #$7e
4023 
tinc4   sta zpt,x
4024 
        set_stat 0
4025 
        inc zpt,x
4026 
        tst_zx rINC,fINC,0
4027 
        lda zpt,x
4028 
        inx
4029 
        cpx #2
4030 
        bne tinc5
4031 
        lda #$fe
4032 
tinc5   cpx #5
4033 
        bne tinc4
4034 
        dex
4035 
        lda #2
4036 
tdec4   sta zpt,x
4037 
        set_stat 0
4038 
        dec zpt,x
4039 
        tst_zx rINC,fINC,0
4040 
        lda zpt,x
4041 
        dex
4042 
        bmi tdec5
4043 
        cpx #1
4044 
        bne tdec4
4045 
        lda #$81
4046 
        bne tdec4
4047 
tdec5
4048 
        ldx #0
4049 
        lda #$7e
4050 
tinc14  sta zpt,x
4051 
        set_stat $ff
4052 
        inc zpt,x
4053 
        tst_zx rINC,fINC,$ff-fnz
4054 
        lda zpt,x
4055 
        inx
4056 
        cpx #2
4057 
        bne tinc15
4058 
        lda #$fe
4059 
tinc15  cpx #5
4060 
        bne tinc14
4061 
        dex
4062 
        lda #2
4063 
tdec14  sta zpt,x
4064 
        set_stat $ff
4065 
        dec zpt,x
4066 
        tst_zx rINC,fINC,$ff-fnz
4067 
        lda zpt,x
4068 
        dex
4069 
        bmi tdec15
4070 
        cpx #1
4071 
        bne tdec14
4072 
        lda #$81
4073 
        bne tdec14
4074 
tdec15
4075 
 
4076 
; memory indexed
4077 
        ldx #0
4078 
        lda #$7e
4079 
tinc6   sta abst,x
4080 
        set_stat 0
4081 
        inc abst,x
4082 
        tst_absx rINC,fINC,0
4083 
        lda abst,x
4084 
        inx
4085 
        cpx #2
4086 
        bne tinc7
4087 
        lda #$fe
4088 
tinc7   cpx #5
4089 
        bne tinc6
4090 
        dex
4091 
        lda #2
4092 
tdec6   sta abst,x
4093 
        set_stat 0
4094 
        dec abst,x
4095 
        tst_absx rINC,fINC,0
4096 
        lda abst,x
4097 
        dex
4098 
        bmi tdec7
4099 
        cpx #1
4100 
        bne tdec6
4101 
        lda #$81
4102 
        bne tdec6
4103 
tdec7
4104 
        ldx #0
4105 
        lda #$7e
4106 
tinc16  sta abst,x
4107 
        set_stat $ff
4108 
        inc abst,x
4109 
        tst_absx rINC,fINC,$ff-fnz
4110 
        lda abst,x
4111 
        inx
4112 
        cpx #2
4113 
        bne tinc17
4114 
        lda #$fe
4115 
tinc17  cpx #5
4116 
        bne tinc16
4117 
        dex
4118 
        lda #2
4119 
tdec16  sta abst,x
4120 
        set_stat $ff
4121 
        dec abst,x
4122 
        tst_absx rINC,fINC,$ff-fnz
4123 
        lda abst,x
4124 
        dex
4125 
        bmi tdec17
4126 
        cpx #1
4127 
        bne tdec16
4128 
        lda #$81
4129 
        bne tdec16
4130 
tdec17
4131 
 
4132 
; testing logical instructions - AND EOR ORA all addressing modes
4133 
; AND
4134 
        ldx #3      ;immediate - self modifying code
4135 
tand    lda zpAN,x
4136 
        sta tandi1
4137 
        set_ax  absANa,0
4138 
tandi1  equ *+1     ;target for immediate operand
4139 
        and #99
4140 
        tst_ax  absrlo,absflo,0
4141 
        dex
4142 
        bpl tand
4143 
        ldx #3
4144 
tand1   lda zpAN,x
4145 
        sta tandi2
4146 
        set_ax  absANa,$ff
4147 
tandi2  equ *+1     ;target for immediate operand
4148 
        and #99
4149 
        tst_ax  absrlo,absflo,$ff-fnz
4150 
        dex
4151 
        bpl tand1
4152 
 
4153 
        ldx #3      ;zp
4154 
tand2    lda zpAN,x
4155 
        sta zpt
4156 
        set_ax  absANa,0
4157 
        and zpt
4158 
        tst_ax  absrlo,absflo,0
4159 
        dex
4160 
        bpl tand2
4161 
        ldx #3
4162 
tand3   lda zpAN,x
4163 
        sta zpt
4164 
        set_ax  absANa,$ff
4165 
        and zpt
4166 
        tst_ax  absrlo,absflo,$ff-fnz
4167 
        dex
4168 
        bpl tand3
4169 
 
4170 
        ldx #3      ;abs
4171 
tand4   lda zpAN,x
4172 
        sta abst
4173 
        set_ax  absANa,0
4174 
        and abst
4175 
        tst_ax  absrlo,absflo,0
4176 
        dex
4177 
        bpl tand4
4178 
        ldx #3
4179 
tand5   lda zpAN,x
4180 
        sta abst
4181 
        set_ax  absANa,$ff
4182 
        and abst
4183 
        tst_ax  absrlo,absflo,$ff-fnz
4184 
        dex
4185 
        bpl tand6
4186 
 
4187 
        ldx #3      ;zp,x
4188 
tand6
4189 
        set_ax  absANa,0
4190 
        and zpAN,x
4191 
        tst_ax  absrlo,absflo,0
4192 
        dex
4193 
        bpl tand6
4194 
        ldx #3
4195 
tand7
4196 
        set_ax  absANa,$ff
4197 
        and zpAN,x
4198 
        tst_ax  absrlo,absflo,$ff-fnz
4199 
        dex
4200 
        bpl tand7
4201 
 
4202 
        ldx #3      ;abs,x
4203 
tand8
4204 
        set_ax  absANa,0
4205 
        and absAN,x
4206 
        tst_ax  absrlo,absflo,0
4207 
        dex
4208 
        bpl tand8
4209 
        ldx #3
4210 
tand9
4211 
        set_ax  absANa,$ff
4212 
        and absAN,x
4213 
        tst_ax  absrlo,absflo,$ff-fnz
4214 
        dex
4215 
        bpl tand9
4216 
 
4217 
        ldy #3      ;abs,y
4218 
tand10
4219 
        set_ay  absANa,0
4220 
        and absAN,y
4221 
        tst_ay  absrlo,absflo,0
4222 
        dey
4223 
        bpl tand10
4224 
        ldy #3
4225 
tand11
4226 
        set_ay  absANa,$ff
4227 
        and absAN,y
4228 
        tst_ay  absrlo,absflo,$ff-fnz
4229 
        dey
4230 
        bpl tand11
4231 
 
4232 
        ldx #6      ;(zp,x)
4233 
        ldy #3
4234 
tand12
4235 
        set_ay  absANa,0
4236 
        and (indAN,x)
4237 
        tst_ay  absrlo,absflo,0
4238 
        dex
4239 
        dex
4240 
        dey
4241 
        bpl tand12
4242 
        ldx #6
4243 
        ldy #3
4244 
tand13
4245 
        set_ay  absANa,$ff
4246 
        and (indAN,x)
4247 
        tst_ay  absrlo,absflo,$ff-fnz
4248 
        dex
4249 
        dex
4250 
        dey
4251 
        bpl tand13
4252 
 
4253 
        ldy #3      ;(zp),y
4254 
tand14
4255 
        set_ay  absANa,0
4256 
        and (indAN),y
4257 
        tst_ay  absrlo,absflo,0
4258 
        dey
4259 
        bpl tand14
4260 
        ldy #3
4261 
tand15
4262 
        set_ay  absANa,$ff
4263 
        and (indAN),y
4264 
        tst_ay  absrlo,absflo,$ff-fnz
4265 
        dey
4266 
        bpl tand15
4267 
 
4268 
; EOR
4269 
        ldx #3      ;immediate - self modifying code
4270 
teor    lda zpEO,x
4271 
        sta teori1
4272 
        set_ax  absEOa,0
4273 
teori1  equ *+1     ;target for immediate operand
4274 
        eor #99
4275 
        tst_ax  absrlo,absflo,0
4276 
        dex
4277 
        bpl teor
4278 
        ldx #3
4279 
teor1   lda zpEO,x
4280 
        sta teori2
4281 
        set_ax  absEOa,$ff
4282 
teori2  equ *+1     ;target for immediate operand
4283 
        eor #99
4284 
        tst_ax  absrlo,absflo,$ff-fnz
4285 
        dex
4286 
        bpl teor1
4287 
 
4288 
        ldx #3      ;zp
4289 
teor2    lda zpEO,x
4290 
        sta zpt
4291 
        set_ax  absEOa,0
4292 
        eor zpt
4293 
        tst_ax  absrlo,absflo,0
4294 
        dex
4295 
        bpl teor2
4296 
        ldx #3
4297 
teor3   lda zpEO,x
4298 
        sta zpt
4299 
        set_ax  absEOa,$ff
4300 
        eor zpt
4301 
        tst_ax  absrlo,absflo,$ff-fnz
4302 
        dex
4303 
        bpl teor3
4304 
 
4305 
        ldx #3      ;abs
4306 
teor4   lda zpEO,x
4307 
        sta abst
4308 
        set_ax  absEOa,0
4309 
        eor abst
4310 
        tst_ax  absrlo,absflo,0
4311 
        dex
4312 
        bpl teor4
4313 
        ldx #3
4314 
teor5   lda zpEO,x
4315 
        sta abst
4316 
        set_ax  absEOa,$ff
4317 
        eor abst
4318 
        tst_ax  absrlo,absflo,$ff-fnz
4319 
        dex
4320 
        bpl teor6
4321 
 
4322 
        ldx #3      ;zp,x
4323 
teor6
4324 
        set_ax  absEOa,0
4325 
        eor zpEO,x
4326 
        tst_ax  absrlo,absflo,0
4327 
        dex
4328 
        bpl teor6
4329 
        ldx #3
4330 
teor7
4331 
        set_ax  absEOa,$ff
4332 
        eor zpEO,x
4333 
        tst_ax  absrlo,absflo,$ff-fnz
4334 
        dex
4335 
        bpl teor7
4336 
 
4337 
        ldx #3      ;abs,x
4338 
teor8
4339 
        set_ax  absEOa,0
4340 
        eor absEO,x
4341 
        tst_ax  absrlo,absflo,0
4342 
        dex
4343 
        bpl teor8
4344 
        ldx #3
4345 
teor9
4346 
        set_ax  absEOa,$ff
4347 
        eor absEO,x
4348 
        tst_ax  absrlo,absflo,$ff-fnz
4349 
        dex
4350 
        bpl teor9
4351 
 
4352 
        ldy #3      ;abs,y
4353 
teor10
4354 
        set_ay  absEOa,0
4355 
        eor absEO,y
4356 
        tst_ay  absrlo,absflo,0
4357 
        dey
4358 
        bpl teor10
4359 
        ldy #3
4360 
teor11
4361 
        set_ay  absEOa,$ff
4362 
        eor absEO,y
4363 
        tst_ay  absrlo,absflo,$ff-fnz
4364 
        dey
4365 
        bpl teor11
4366 
 
4367 
        ldx #6      ;(zp,x)
4368 
        ldy #3
4369 
teor12
4370 
        set_ay  absEOa,0
4371 
        eor (indEO,x)
4372 
        tst_ay  absrlo,absflo,0
4373 
        dex
4374 
        dex
4375 
        dey
4376 
        bpl teor12
4377 
        ldx #6
4378 
        ldy #3
4379 
teor13
4380 
        set_ay  absEOa,$ff
4381 
        eor (indEO,x)
4382 
        tst_ay  absrlo,absflo,$ff-fnz
4383 
        dex
4384 
        dex
4385 
        dey
4386 
        bpl teor13
4387 
 
4388 
        ldy #3      ;(zp),y
4389 
teor14
4390 
        set_ay  absEOa,0
4391 
        eor (indEO),y
4392 
        tst_ay  absrlo,absflo,0
4393 
        dey
4394 
        bpl teor14
4395 
        ldy #3
4396 
teor15
4397 
        set_ay  absEOa,$ff
4398 
        eor (indEO),y
4399 
        tst_ay  absrlo,absflo,$ff-fnz
4400 
        dey
4401 
        bpl teor15
4402 
 
4403 
; OR
4404 
        ldx #3      ;immediate - self modifying code
4405 
tora    lda zpOR,x
4406 
        sta torai1
4407 
        set_ax  absORa,0
4408 
torai1  equ *+1     ;target for immediate operand
4409 
        ora #99
4410 
        tst_ax  absrlo,absflo,0
4411 
        dex
4412 
        bpl tora
4413 
        ldx #3
4414 
tora1   lda zpOR,x
4415 
        sta torai2
4416 
        set_ax  absORa,$ff
4417 
torai2  equ *+1     ;target for immediate operand
4418 
        ora #99
4419 
        tst_ax  absrlo,absflo,$ff-fnz
4420 
        dex
4421 
        bpl tora1
4422 
 
4423 
        ldx #3      ;zp
4424 
tora2    lda zpOR,x
4425 
        sta zpt
4426 
        set_ax  absORa,0
4427 
        ora zpt
4428 
        tst_ax  absrlo,absflo,0
4429 
        dex
4430 
        bpl tora2
4431 
        ldx #3
4432 
tora3   lda zpOR,x
4433 
        sta zpt
4434 
        set_ax  absORa,$ff
4435 
        ora zpt
4436 
        tst_ax  absrlo,absflo,$ff-fnz
4437 
        dex
4438 
        bpl tora3
4439 
 
4440 
        ldx #3      ;abs
4441 
tora4   lda zpOR,x
4442 
        sta abst
4443 
        set_ax  absORa,0
4444 
        ora abst
4445 
        tst_ax  absrlo,absflo,0
4446 
        dex
4447 
        bpl tora4
4448 
        ldx #3
4449 
tora5   lda zpOR,x
4450 
        sta abst
4451 
        set_ax  absORa,$ff
4452 
        ora abst
4453 
        tst_ax  absrlo,absflo,$ff-fnz
4454 
        dex
4455 
        bpl tora6
4456 
 
4457 
        ldx #3      ;zp,x
4458 
tora6
4459 
        set_ax  absORa,0
4460 
        ora zpOR,x
4461 
        tst_ax  absrlo,absflo,0
4462 
        dex
4463 
        bpl tora6
4464 
        ldx #3
4465 
tora7
4466 
        set_ax  absORa,$ff
4467 
        ora zpOR,x
4468 
        tst_ax  absrlo,absflo,$ff-fnz
4469 
        dex
4470 
        bpl tora7
4471 
 
4472 
        ldx #3      ;abs,x
4473 
tora8
4474 
        set_ax  absORa,0
4475 
        ora absOR,x
4476 
        tst_ax  absrlo,absflo,0
4477 
        dex
4478 
        bpl tora8
4479 
        ldx #3
4480 
tora9
4481 
        set_ax  absORa,$ff
4482 
        ora absOR,x
4483 
        tst_ax  absrlo,absflo,$ff-fnz
4484 
        dex
4485 
        bpl tora9
4486 
 
4487 
        ldy #3      ;abs,y
4488 
tora10
4489 
        set_ay  absORa,0
4490 
        ora absOR,y
4491 
        tst_ay  absrlo,absflo,0
4492 
        dey
4493 
        bpl tora10
4494 
        ldy #3
4495 
tora11
4496 
        set_ay  absORa,$ff
4497 
        ora absOR,y
4498 
        tst_ay  absrlo,absflo,$ff-fnz
4499 
        dey
4500 
        bpl tora11
4501 
 
4502 
        ldx #6      ;(zp,x)
4503 
        ldy #3
4504 
tora12
4505 
        set_ay  absORa,0
4506 
        ora (indOR,x)
4507 
        tst_ay  absrlo,absflo,0
4508 
        dex
4509 
        dex
4510 
        dey
4511 
        bpl tora12
4512 
        ldx #6
4513 
        ldy #3
4514 
tora13
4515 
        set_ay  absORa,$ff
4516 
        ora (indOR,x)
4517 
        tst_ay  absrlo,absflo,$ff-fnz
4518 
        dex
4519 
        dex
4520 
        dey
4521 
        bpl tora13
4522 
 
4523 
        ldy #3      ;(zp),y
4524 
tora14
4525 
        set_ay  absORa,0
4526 
        ora (indOR),y
4527 
        tst_ay  absrlo,absflo,0
4528 
        dey
4529 
        bpl tora14
4530 
        ldy #3
4531 
tora15
4532 
        set_ay  absORa,$ff
4533 
        ora (indOR),y
4534 
        tst_ay  absrlo,absflo,$ff-fnz
4535 
        dey
4536 
        bpl tora15
4537 
    if I_flag = 3
4538 
        cli
4539 
    endif
4540 
 
4541 
; full binary add/subtract test
4542 
; iterates through all combinations of operands and carry input
4543 
; uses increments/decrements to predict result & result flags
4544 
        cld
4545 
        ldx #ad2        ;for indexed test
4546 
        ldy #$ff        ;max range
4547 
        lda #0          ;start with adding zeroes & no carry
4548 
        sta adfc        ;carry in - for diag
4549 
        sta ad1         ;operand 1 - accumulator
4550 
        sta ad2         ;operand 2 - memory or immediate
4551 
        sta ada2        ;non zp
4552 
        sta adrl        ;expected result bits 0-7
4553 
        sta adrh        ;expected result bit 8 (carry out)
4554 
        lda #$ff        ;complemented operand 2 for subtract
4555 
        sta sb2
4556 
        sta sba2        ;non zp
4557 
        lda #2          ;expected Z-flag
4558 
        sta adrf
4559 
tadd    clc             ;test with carry clear
4560 
        jsr chkadd
4561 
        inc adfc        ;now with carry
4562 
        inc adrl        ;result +1
4563 
        php             ;save N & Z from low result
4564 
        php
4565 
        pla             ;accu holds expected flags
4566 
        and #$82        ;mask N & Z
4567 
        plp
4568 
        bne tadd1
4569 
        inc adrh        ;result bit 8 - carry
4570 
tadd1   ora adrh        ;merge C to expected flags
4571 
        sta adrf        ;save expected flags except overflow
4572 
        sec             ;test with carry set
4573 
        jsr chkadd
4574 
        dec adfc        ;same for operand +1 but no carry
4575 
        inc ad1
4576 
        bne tadd        ;iterate op1
4577 
        lda #0          ;preset result to op2 when op1 = 0
4578 
        sta adrh
4579 
        inc ada2
4580 
        inc ad2
4581 
        php             ;save NZ as operand 2 becomes the new result
4582 
        pla
4583 
        and #$82        ;mask N00000Z0
4584 
        sta adrf        ;no need to check carry as we are adding to 0
4585 
        dec sb2         ;complement subtract operand 2
4586 
        dec sba2
4587 
        lda ad2
4588 
        sta adrl
4589 
        bne tadd        ;iterate op2
4590 
 
4591 
; decimal add/subtract test
4592 
; *** WARNING - tests documented behavior only! ***
4593 
;   only valid BCD operands are tested, N V Z flags are ignored
4594 
; iterates through all valid combinations of operands and carry input
4595 
; uses increments/decrements to predict result & carry flag
4596 
        sed
4597 
        ldx #ad2        ;for indexed test
4598 
        ldy #$ff        ;max range
4599 
        lda #$99        ;start with adding 99 to 99 with carry
4600 
        sta ad1         ;operand 1 - accumulator
4601 
        sta ad2         ;operand 2 - memory or immediate
4602 
        sta ada2        ;non zp
4603 
        sta adrl        ;expected result bits 0-7
4604 
        lda #1          ;set carry in & out
4605 
        sta adfc        ;carry in - for diag
4606 
        sta adrh        ;expected result bit 8 (carry out)
4607 
        lda #0          ;complemented operand 2 for subtract
4608 
        sta sb2
4609 
        sta sba2        ;non zp
4610 
tdad    sec             ;test with carry set
4611 
        jsr chkdad
4612 
        dec adfc        ;now with carry clear
4613 
        lda adrl        ;decimal adjust result
4614 
        bne tdad1       ;skip clear carry & preset result 99 (9A-1)
4615 
        dec adrh
4616 
        lda #$99
4617 
        sta adrl
4618 
        bne tdad3
4619 
tdad1   and #$f         ;lower nibble mask
4620 
        bne tdad2       ;no decimal adjust needed
4621 
        dec adrl        ;decimal adjust (?0-6)
4622 
        dec adrl
4623 
        dec adrl
4624 
        dec adrl
4625 
        dec adrl
4626 
        dec adrl
4627 
tdad2   dec adrl        ;result -1
4628 
tdad3   clc             ;test with carry clear
4629 
        jsr chkdad
4630 
        inc adfc        ;same for operand -1 but with carry
4631 
        lda ad1         ;decimal adjust operand 1
4632 
        beq tdad5       ;iterate operand 2
4633 
        and #$f         ;lower nibble mask
4634 
        bne tdad4       ;skip decimal adjust
4635 
        dec ad1         ;decimal adjust (?0-6)
4636 
        dec ad1
4637 
        dec ad1
4638 
        dec ad1
4639 
        dec ad1
4640 
        dec ad1
4641 
tdad4   dec ad1         ;operand 1 -1
4642 
        jmp tdad        ;iterate op1
4643 
 
4644 
tdad5   lda #$99        ;precharge op1 max
4645 
        sta ad1
4646 
        lda ad2         ;decimal adjust operand 2
4647 
        beq tdad7       ;end of iteration
4648 
        and #$f         ;lower nibble mask
4649 
        bne tdad6       ;skip decimal adjust
4650 
        dec ad2         ;decimal adjust (?0-6)
4651 
        dec ad2
4652 
        dec ad2
4653 
        dec ad2
4654 
        dec ad2
4655 
        dec ad2
4656 
        inc sb2         ;complemented decimal adjust for subtract (?9+6)
4657 
        inc sb2
4658 
        inc sb2
4659 
        inc sb2
4660 
        inc sb2
4661 
        inc sb2
4662 
tdad6   dec ad2         ;operand 2 -1
4663 
        inc sb2         ;complemeted operand for subtract
4664 
        lda sb2
4665 
        sta sba2        ;copy as non zp operand
4666 
        lda ad2
4667 
        sta ada2        ;copy as non zp operand
4668 
        sta adrl        ;new result since op1+carry=00+carry +op2=op2
4669 
        inc adrh        ;result carry
4670 
        bne tdad        ;iterate op2
4671 
tdad7   cld
4672 
 
4673 
 
4674 
        lda #$ff
4675 
        sta $8002
4676 
 
4677 
; S U C C E S S ************************************************
4678 
; -------------
4679 
        success         ;if you get here everything went well
4680 
; -------------
4681 
; S U C C E S S ************************************************
4682 
 
4683 
; core subroutine of the decimal add/subtract test
4684 
; *** WARNING - tests documented behavior only! ***
4685 
;   only valid BCD operands are tested, N V Z flags are ignored
4686 
; iterates through all valid combinations of operands and carry input
4687 
; uses increments/decrements to predict result & carry flag
4688 
chkdad
4689 
; decimal ADC / SBC zp
4690 
        php             ;save carry for subtract
4691 
        lda ad1
4692 
        adc ad2         ;perform add
4693 
        php
4694 
        cmp adrl        ;check result
4695 
        trap_ne         ;bad result
4696 
        pla             ;check flags
4697 
        and #1          ;mask carry
4698 
        cmp adrh
4699 
        trap_ne         ;bad carry
4700 
        plp
4701 
        php             ;save carry for next add
4702 
        lda ad1
4703 
        sbc sb2         ;perform subtract
4704 
        php
4705 
        cmp adrl        ;check result
4706 
        trap_ne         ;bad result
4707 
        pla             ;check flags
4708 
        and #1          ;mask carry
4709 
        cmp adrh
4710 
        trap_ne         ;bad flags
4711 
        plp
4712 
; decimal ADC / SBC abs
4713 
        php             ;save carry for subtract
4714 
        lda ad1
4715 
        adc ada2        ;perform add
4716 
        php
4717 
        cmp adrl        ;check result
4718 
        trap_ne         ;bad result
4719 
        pla             ;check flags
4720 
        and #1          ;mask carry
4721 
        cmp adrh
4722 
        trap_ne         ;bad carry
4723 
        plp
4724 
        php             ;save carry for next add
4725 
        lda ad1
4726 
        sbc sba2        ;perform subtract
4727 
        php
4728 
        cmp adrl        ;check result
4729 
        trap_ne         ;bad result
4730 
        pla             ;check flags
4731 
        and #1          ;mask carry
4732 
        cmp adrh
4733 
        trap_ne         ;bad carry
4734 
        plp
4735 
; decimal ADC / SBC #
4736 
        php             ;save carry for subtract
4737 
        lda ad2
4738 
        sta chkdadi     ;self modify immediate
4739 
        lda ad1
4740 
chkdadi = * + 1         ;operand of the immediate ADC
4741 
        adc #0          ;perform add
4742 
        php
4743 
        cmp adrl        ;check result
4744 
        trap_ne         ;bad result
4745 
        pla             ;check flags
4746 
        and #1          ;mask carry
4747 
        cmp adrh
4748 
        trap_ne         ;bad carry
4749 
        plp
4750 
        php             ;save carry for next add
4751 
        lda sb2
4752 
        sta chkdsbi     ;self modify immediate
4753 
        lda ad1
4754 
chkdsbi = * + 1         ;operand of the immediate SBC
4755 
        sbc #0          ;perform subtract
4756 
        php
4757 
        cmp adrl        ;check result
4758 
        trap_ne         ;bad result
4759 
        pla             ;check flags
4760 
        and #1          ;mask carry
4761 
        cmp adrh
4762 
        trap_ne         ;bad carry
4763 
        plp
4764 
; decimal ADC / SBC zp,x
4765 
        php             ;save carry for subtract
4766 
        lda ad1
4767 
        adc 0,x         ;perform add
4768 
        php
4769 
        cmp adrl        ;check result
4770 
        trap_ne         ;bad result
4771 
        pla             ;check flags
4772 
        and #1          ;mask carry
4773 
        cmp adrh
4774 
        trap_ne         ;bad carry
4775 
        plp
4776 
        php             ;save carry for next add
4777 
        lda ad1
4778 
        sbc sb2-ad2,x   ;perform subtract
4779 
        php
4780 
        cmp adrl        ;check result
4781 
        trap_ne         ;bad result
4782 
        pla             ;check flags
4783 
        and #1          ;mask carry
4784 
        cmp adrh
4785 
        trap_ne         ;bad carry
4786 
        plp
4787 
; decimal ADC / SBC abs,x
4788 
        php             ;save carry for subtract
4789 
        lda ad1
4790 
        adc ada2-ad2,x  ;perform add
4791 
        php
4792 
        cmp adrl        ;check result
4793 
        trap_ne         ;bad result
4794 
        pla             ;check flags
4795 
        and #1          ;mask carry
4796 
        cmp adrh
4797 
        trap_ne         ;bad carry
4798 
        plp
4799 
        php             ;save carry for next add
4800 
        lda ad1
4801 
        sbc sba2-ad2,x  ;perform subtract
4802 
        php
4803 
        cmp adrl        ;check result
4804 
        trap_ne         ;bad result
4805 
        pla             ;check flags
4806 
        and #1          ;mask carry
4807 
        cmp adrh
4808 
        trap_ne         ;bad carry
4809 
        plp
4810 
; decimal ADC / SBC abs,y
4811 
        php             ;save carry for subtract
4812 
        lda ad1
4813 
        adc ada2-$ff,y  ;perform add
4814 
        php
4815 
        cmp adrl        ;check result
4816 
        trap_ne         ;bad result
4817 
        pla             ;check flags
4818 
        and #1          ;mask carry
4819 
        cmp adrh
4820 
        trap_ne         ;bad carry
4821 
        plp
4822 
        php             ;save carry for next add
4823 
        lda ad1
4824 
        sbc sba2-$ff,y  ;perform subtract
4825 
        php
4826 
        cmp adrl        ;check result
4827 
        trap_ne         ;bad result
4828 
        pla             ;check flags
4829 
        and #1          ;mask carry
4830 
        cmp adrh
4831 
        trap_ne         ;bad carry
4832 
        plp
4833 
; decimal ADC / SBC (zp,x)
4834 
        php             ;save carry for subtract
4835 
        lda ad1
4836 
        adc (lo adi2-ad2,x) ;perform add
4837 
        php
4838 
        cmp adrl        ;check result
4839 
        trap_ne         ;bad result
4840 
        pla             ;check flags
4841 
        and #1          ;mask carry
4842 
        cmp adrh
4843 
        trap_ne         ;bad carry
4844 
        plp
4845 
        php             ;save carry for next add
4846 
        lda ad1
4847 
        sbc (lo sbi2-ad2,x) ;perform subtract
4848 
        php
4849 
        cmp adrl        ;check result
4850 
        trap_ne         ;bad result
4851 
        pla             ;check flags
4852 
        and #1          ;mask carry
4853 
        cmp adrh
4854 
        trap_ne         ;bad carry
4855 
        plp
4856 
; decimal ADC / SBC (abs),y
4857 
        php             ;save carry for subtract
4858 
        lda ad1
4859 
        adc (adiy2),y   ;perform add
4860 
        php
4861 
        cmp adrl        ;check result
4862 
        trap_ne         ;bad result
4863 
        pla             ;check flags
4864 
        and #1          ;mask carry
4865 
        cmp adrh
4866 
        trap_ne         ;bad carry
4867 
        plp
4868 
        php             ;save carry for next add
4869 
        lda ad1
4870 
        sbc (sbiy2),y   ;perform subtract
4871 
        php
4872 
        cmp adrl        ;check result
4873 
        trap_ne         ;bad result
4874 
        pla             ;check flags
4875 
        and #1          ;mask carry
4876 
        cmp adrh
4877 
        trap_ne         ;bad carry
4878 
        plp
4879 
        rts
4880 
 
4881 
; core subroutine of the full binary add/subtract test
4882 
; iterates through all combinations of operands and carry input
4883 
; uses increments/decrements to predict result & result flags
4884 
chkadd  lda adrf        ;add V-flag if overflow
4885 
        and #$83        ;keep N-----ZC / clear V
4886 
        pha
4887 
        lda ad1         ;test sign unequal between operands
4888 
        eor ad2
4889 
        bmi ckad1       ;no overflow possible - operands have different sign
4890 
        lda ad1         ;test sign equal between operands and result
4891 
        eor adrl
4892 
        bpl ckad1       ;no overflow occured - operand and result have same sign
4893 
        pla
4894 
        ora #$40        ;set V
4895 
        pha
4896 
ckad1   pla
4897 
        sta adrf        ;save expected flags
4898 
; binary ADC / SBC zp
4899 
        php             ;save carry for subtract
4900 
        lda ad1
4901 
        adc ad2         ;perform add
4902 
        php
4903 
        cmp adrl        ;check result
4904 
        trap_ne         ;bad result
4905 
        pla             ;check flags
4906 
        and #$c3        ;mask NV----ZC
4907 
        cmp adrf
4908 
        trap_ne         ;bad flags
4909 
        plp
4910 
        php             ;save carry for next add
4911 
        lda ad1
4912 
        sbc sb2         ;perform subtract
4913 
        php
4914 
        cmp adrl        ;check result
4915 
        trap_ne         ;bad result
4916 
        pla             ;check flags
4917 
        and #$c3        ;mask NV----ZC
4918 
        cmp adrf
4919 
        trap_ne         ;bad flags
4920 
        plp
4921 
; binary ADC / SBC abs
4922 
        php             ;save carry for subtract
4923 
        lda ad1
4924 
        adc ada2        ;perform add
4925 
        php
4926 
        cmp adrl        ;check result
4927 
        trap_ne         ;bad result
4928 
        pla             ;check flags
4929 
        and #$c3        ;mask NV----ZC
4930 
        cmp adrf
4931 
        trap_ne         ;bad flags
4932 
        plp
4933 
        php             ;save carry for next add
4934 
        lda ad1
4935 
        sbc sba2        ;perform subtract
4936 
        php
4937 
        cmp adrl        ;check result
4938 
        trap_ne         ;bad result
4939 
        pla             ;check flags
4940 
        and #$c3        ;mask NV----ZC
4941 
        cmp adrf
4942 
        trap_ne         ;bad flags
4943 
        plp
4944 
; binary ADC / SBC #
4945 
        php             ;save carry for subtract
4946 
        lda ad2
4947 
        sta chkadi      ;self modify immediate
4948 
        lda ad1
4949 
chkadi  = * + 1         ;operand of the immediate ADC
4950 
        adc #0          ;perform add
4951 
        php
4952 
        cmp adrl        ;check result
4953 
        trap_ne         ;bad result
4954 
        pla             ;check flags
4955 
        and #$c3        ;mask NV----ZC
4956 
        cmp adrf
4957 
        trap_ne         ;bad flags
4958 
        plp
4959 
        php             ;save carry for next add
4960 
        lda sb2
4961 
        sta chksbi      ;self modify immediate
4962 
        lda ad1
4963 
chksbi  = * + 1         ;operand of the immediate SBC
4964 
        sbc #0          ;perform subtract
4965 
        php
4966 
        cmp adrl        ;check result
4967 
        trap_ne         ;bad result
4968 
        pla             ;check flags
4969 
        and #$c3        ;mask NV----ZC
4970 
        cmp adrf
4971 
        trap_ne         ;bad flags
4972 
        plp
4973 
; binary ADC / SBC zp,x
4974 
        php             ;save carry for subtract
4975 
        lda ad1
4976 
        adc 0,x         ;perform add
4977 
        php
4978 
        cmp adrl        ;check result
4979 
        trap_ne         ;bad result
4980 
        pla             ;check flags
4981 
        and #$c3        ;mask NV----ZC
4982 
        cmp adrf
4983 
        trap_ne         ;bad flags
4984 
        plp
4985 
        php             ;save carry for next add
4986 
        lda ad1
4987 
        sbc sb2-ad2,x   ;perform subtract
4988 
        php
4989 
        cmp adrl        ;check result
4990 
        trap_ne         ;bad result
4991 
        pla             ;check flags
4992 
        and #$c3        ;mask NV----ZC
4993 
        cmp adrf
4994 
        trap_ne         ;bad flags
4995 
        plp
4996 
; binary ADC / SBC abs,x
4997 
        php             ;save carry for subtract
4998 
        lda ad1
4999 
        adc ada2-ad2,x  ;perform add
5000 
        php
5001 
        cmp adrl        ;check result
5002 
        trap_ne         ;bad result
5003 
        pla             ;check flags
5004 
        and #$c3        ;mask NV----ZC
5005 
        cmp adrf
5006 
        trap_ne         ;bad flags
5007 
        plp
5008 
        php             ;save carry for next add
5009 
        lda ad1
5010 
        sbc sba2-ad2,x  ;perform subtract
5011 
        php
5012 
        cmp adrl        ;check result
5013 
        trap_ne         ;bad result
5014 
        pla             ;check flags
5015 
        and #$c3        ;mask NV----ZC
5016 
        cmp adrf
5017 
        trap_ne         ;bad flags
5018 
        plp
5019 
; binary ADC / SBC abs,y
5020 
        php             ;save carry for subtract
5021 
        lda ad1
5022 
        adc ada2-$ff,y  ;perform add
5023 
        php
5024 
        cmp adrl        ;check result
5025 
        trap_ne         ;bad result
5026 
        pla             ;check flags
5027 
        and #$c3        ;mask NV----ZC
5028 
        cmp adrf
5029 
        trap_ne         ;bad flags
5030 
        plp
5031 
        php             ;save carry for next add
5032 
        lda ad1
5033 
        sbc sba2-$ff,y  ;perform subtract
5034 
        php
5035 
        cmp adrl        ;check result
5036 
        trap_ne         ;bad result
5037 
        pla             ;check flags
5038 
        and #$c3        ;mask NV----ZC
5039 
        cmp adrf
5040 
        trap_ne         ;bad flags
5041 
        plp
5042 
; binary ADC / SBC (zp,x)
5043 
        php             ;save carry for subtract
5044 
        lda ad1
5045 
        adc (lo adi2-ad2,x) ;perform add
5046 
        php
5047 
        cmp adrl        ;check result
5048 
        trap_ne         ;bad result
5049 
        pla             ;check flags
5050 
        and #$c3        ;mask NV----ZC
5051 
        cmp adrf
5052 
        trap_ne         ;bad flags
5053 
        plp
5054 
        php             ;save carry for next add
5055 
        lda ad1
5056 
        sbc (lo sbi2-ad2,x) ;perform subtract
5057 
        php
5058 
        cmp adrl        ;check result
5059 
        trap_ne         ;bad result
5060 
        pla             ;check flags
5061 
        and #$c3        ;mask NV----ZC
5062 
        cmp adrf
5063 
        trap_ne         ;bad flags
5064 
        plp
5065 
; binary ADC / SBC (abs),y
5066 
        php             ;save carry for subtract
5067 
        lda ad1
5068 
        adc (adiy2),y   ;perform add
5069 
        php
5070 
        cmp adrl        ;check result
5071 
        trap_ne         ;bad result
5072 
        pla             ;check flags
5073 
        and #$c3        ;mask NV----ZC
5074 
        cmp adrf
5075 
        trap_ne         ;bad flags
5076 
        plp
5077 
        php             ;save carry for next add
5078 
        lda ad1
5079 
        sbc (sbiy2),y   ;perform subtract
5080 
        php
5081 
        cmp adrl        ;check result
5082 
        trap_ne         ;bad result
5083 
        pla             ;check flags
5084 
        and #$c3        ;mask NV----ZC
5085 
        cmp adrf
5086 
        trap_ne         ;bad flags
5087 
        plp
5088 
        rts
5089 
 
5090 
; target for the jump absolute test
5091 
        dey
5092 
        dey
5093 
test_far
5094 
        php             ;either SP or Y count will fail, if we do not hit
5095 
        dey
5096 
        dey
5097 
        dey
5098 
        plp
5099 
        trap_cs         ;flags loaded?
5100 
        trap_vs
5101 
        trap_mi
5102 
        trap_eq
5103 
        cmp #'F'        ;registers loaded?
5104 
        trap_ne
5105 
        cpx #'A'
5106 
        trap_ne
5107 
        cpy #('R'-3)
5108 
        trap_ne
5109 
        pha             ;save a,x
5110 
        txa
5111 
        pha
5112 
        tsx
5113 
        cpx #$fd        ;check SP
5114 
        trap_ne
5115 
        pla             ;restore x
5116 
        tax
5117 
        set_stat $ff
5118 
        pla             ;restore a
5119 
        inx             ;return registers with modifications
5120 
        eor #$aa        ;N=1, V=1, Z=0, C=1
5121 
        jmp far_ret
5122 
 
5123 
; target for the jump indirect test
5124 
ptr_tst_ind dw test_ind
5125 
ptr_ind_ret dw ind_ret
5126 
        trap            ;runover protection
5127 
        dey
5128 
        dey
5129 
test_ind
5130 
        php             ;either SP or Y count will fail, if we do not hit
5131 
        dey
5132 
        dey
5133 
        dey
5134 
        plp
5135 
        trap_cs         ;flags loaded?
5136 
        trap_vs
5137 
        trap_mi
5138 
        trap_eq
5139 
        cmp #'I'        ;registers loaded?
5140 
        trap_ne
5141 
        cpx #'N'
5142 
        trap_ne
5143 
        cpy #('D'-3)
5144 
        trap_ne
5145 
        pha             ;save a,x
5146 
        txa
5147 
        pha
5148 
        tsx
5149 
        cpx #$fd        ;check SP
5150 
        trap_ne
5151 
        pla             ;restore x
5152 
        tax
5153 
        set_stat $ff
5154 
        pla             ;restore a
5155 
        inx             ;return registers with modifications
5156 
        eor #$aa        ;N=1, V=1, Z=0, C=1
5157 
        jmp (ptr_ind_ret)
5158 
        trap            ;runover protection
5159 
 
5160 
; target for the jump subroutine test
5161 
        dey
5162 
        dey
5163 
test_jsr
5164 
        php             ;either SP or Y count will fail, if we do not hit
5165 
        dey
5166 
        dey
5167 
        dey
5168 
        plp
5169 
        trap_cs         ;flags loaded?
5170 
        trap_vs
5171 
        trap_mi
5172 
        trap_eq
5173 
        cmp #'J'        ;registers loaded?
5174 
        trap_ne
5175 
        cpx #'S'
5176 
        trap_ne
5177 
        cpy #('R'-3)
5178 
        trap_ne
5179 
        pha             ;save a,x
5180 
        txa
5181 
        pha
5182 
        tsx             ;sp -4? (return addr,a,x)
5183 
        cpx #$fb
5184 
        trap_ne
5185 
        lda $1ff        ;propper return on stack
5186 
        cmp #hi(jsr_ret)
5187 
        trap_ne
5188 
        lda $1fe
5189 
        cmp #lo(jsr_ret)
5190 
        trap_ne
5191 
        set_stat $ff
5192 
        pla             ;pull x,a
5193 
        tax
5194 
        pla
5195 
        inx             ;return registers with modifications
5196 
        eor #$aa        ;N=1, V=1, Z=0, C=1
5197 
        rts
5198 
        trap            ;runover protection
5199 
 
5200 
;trap in case of unexpected IRQ, NMI, BRK, RESET - BRK test target
5201 
nmi_trap
5202 
        trap            ;check stack for conditions at NMI
5203 
res_trap
5204 
        trap            ;unexpected RESET
5205 
 
5206 
        dey
5207 
        dey
5208 
irq_trap                ;BRK test or unextpected BRK or IRQ
5209 
        php             ;either SP or Y count will fail, if we do not hit
5210 
        dey
5211 
        dey
5212 
        dey
5213 
        ;next 4 traps could be caused by unexpected BRK or IRQ
5214 
        ;check stack for BREAK and originating location
5215 
        ;possible jump/branch into weeds (uninitialized space)
5216 
        cmp #'B'        ;registers loaded?
5217 
        trap_ne
5218 
        cpx #'R'
5219 
        trap_ne
5220 
        cpy #('K'-3)
5221 
        trap_ne
5222 
        sta irq_a       ;save registers during break test
5223 
        stx irq_x
5224 
        tsx             ;test break on stack
5225 
        lda $102,x
5226 
        cmp_flag 0      ;break test should have B=1
5227 
        trap_ne         ; - no break flag on stack
5228 
        pla
5229 
        cmp #$34        ;should have added interrupt disable
5230 
        trap_ne
5231 
        tsx
5232 
        cpx #$fc        ;sp -3? (return addr, flags)
5233 
        trap_ne
5234 
        lda $1ff        ;propper return on stack
5235 
        cmp #hi(brk_ret)
5236 
        trap_ne
5237 
        lda $1fe
5238 
        cmp #lo(brk_ret)
5239 
        trap_ne
5240 
        set_stat $ff
5241 
        ldx irq_x
5242 
        inx             ;return registers with modifications
5243 
        lda irq_a
5244 
        eor #$aa        ;N=1, V=1, Z=0, C=1 but original flags should be restored
5245 
        rti
5246 
        trap            ;runover protection
5247 
 
5248 
;copy of data to initialize BSS segment
5249 
    if load_data_direct != 1
5250 
zp_init
5251 
zp1_    db  $c3,$82,$41,0   ;test patterns for LDx BIT ROL ROR ASL LSR
5252 
zp7f_   db  $7f             ;test pattern for compare
5253 
zpt_    ds  5               ;store/modify test area
5254 
;logical zeropage operands
5255 
zpOR_   db  0,$1f,$71,$80   ;test pattern for OR
5256 
zpAN_   db  $0f,$ff,$7f,$80 ;test pattern for AND
5257 
zpEO_   db  $ff,$0f,$8f,$8f ;test pattern for EOR
5258 
;indirect addressing pointers
5259 
ind1_   dw  abs1            ;indirect pointer to pattern in absolute memory
5260 
        dw  abs1+1
5261 
        dw  abs1+2
5262 
        dw  abs1+3
5263 
        dw  abs7f
5264 
inw1_   dw  abs1-$f8        ;indirect pointer for wrap-test pattern
5265 
indt_   dw  abst            ;indirect pointer to store area in absolute memory
5266 
        dw  abst+1
5267 
        dw  abst+2
5268 
        dw  abst+3
5269 
inwt_   dw  abst-$f8        ;indirect pointer for wrap-test store
5270 
indAN_  dw  absAN           ;indirect pointer to AND pattern in absolute memory
5271 
        dw  absAN+1
5272 
        dw  absAN+2
5273 
        dw  absAN+3
5274 
indEO_  dw  absEO           ;indirect pointer to EOR pattern in absolute memory
5275 
        dw  absEO+1
5276 
        dw  absEO+2
5277 
        dw  absEO+3
5278 
indOR_  dw  absOR           ;indirect pointer to OR pattern in absolute memory
5279 
        dw  absOR+1
5280 
        dw  absOR+2
5281 
        dw  absOR+3
5282 
;add/subtract operand generation and result/flag prediction
5283 
adi2_   dw  ada2            ;indirect pointer to operand 2 in absolute memory
5284 
sbi2_   dw  sba2            ;indirect pointer to complemented operand 2 (SBC)
5285 
adiy2_  dw  ada2-$ff        ;with offset for indirect indexed
5286 
sbiy2_  dw  sba2-$ff
5287 
;adfc    ds  1               ;carry flag before op
5288 
;ad1     ds  1               ;operand 1 - accumulator
5289 
;ad2     ds  1               ;operand 2 - memory / immediate
5290 
;adrl    ds  1               ;expected result bits 0-7
5291 
;adrh    ds  1               ;expected result bit 8 (carry)
5292 
;adrf    ds  1               ;expected flags NV0000ZC (not valid in decimal mode)
5293 
;sb2     ds  1               ;operand 2 complemented for subtract
5294 
;break test interrupt save
5295 
;irq_a   ds  1               ;a register
5296 
;irq_x   ds  1               ;x register
5297 
zp_end
5298 
    if (zp_end - zp_init) != (zp_bss_end - zp_bss)
5299 
        ;force assembler error if size is different
5300 
        ERROR ERROR ERROR   ;mismatch between bss and zeropage data
5301 
    endif
5302 
data_init
5303 
abs1_   db  $c3,$82,$41,0   ;test patterns for LDx BIT ROL ROR ASL LSR
5304 
abs7f_  db  $7f             ;test pattern for compare
5305 
;loads
5306 
fLDx_   db  fn,fn,0,fz      ;expected flags for load
5307 
;shifts
5308 
rASL_                       ;expected result ASL & ROL -carry
5309 
rROL_   db  $86,$04,$82,0   ; "
5310 
rROLc_  db  $87,$05,$83,1   ;expected result ROL +carry
5311 
rLSR_                       ;expected result LSR & ROR -carry
5312 
rROR_   db  $61,$41,$20,0   ; "
5313 
rRORc_  db  $e1,$c1,$a0,$80 ;expected result ROR +carry
5314 
fASL_                       ;expected flags for shifts
5315 
fROL_   db  fnc,fc,fn,fz    ;no carry in
5316 
fROLc_  db  fnc,fc,fn,0     ;carry in
5317 
fLSR_
5318 
fROR_   db  fc,0,fc,fz      ;no carry in
5319 
fRORc_  db  fnc,fn,fnc,fn   ;carry in
5320 
;increments (decrements)
5321 
rINC_   db  $7f,$80,$ff,0,1 ;expected result for INC/DEC
5322 
fINC_   db  0,fn,fn,fz,0    ;expected flags for INC/DEC
5323 
abst_   ds  5               ;store/modify test area
5324 
;logical memory operand
5325 
absOR_  db  0,$1f,$71,$80   ;test pattern for OR
5326 
absAN_  db  $0f,$ff,$7f,$80 ;test pattern for AND
5327 
absEO_  db  $ff,$0f,$8f,$8f ;test pattern for EOR
5328 
;logical accu operand
5329 
absORa_ db  0,$f1,$1f,0     ;test pattern for OR
5330 
absANa_ db  $f0,$ff,$ff,$ff ;test pattern for AND
5331 
absEOa_ db  $ff,$f0,$f0,$0f ;test pattern for EOR
5332 
;logical results
5333 
absrlo_ db  0,$ff,$7f,$80
5334 
absflo_ db  fz,fn,0,fn
5335 
;add/subtract operand copy
5336 
;ada2    ds  1               ;operand 2
5337 
;sba2    ds  1               ;operand 2 complemented for subtract
5338 
data_end
5339 
    if (data_end - data_init) != (data_bss_end - data_bss)
5340 
        ;force assembler error if size is different
5341 
        ERROR ERROR ERROR   ;mismatch between bss and data
5342 
    endif
5343 
    endif                   ;end of RAM init data
5344 
 
5345 
    if ROM_vectors = 1
5346 
        org $fffa       ;vectors
5347 
        dw  nmi_trap
5348 
        dw  start
5349 
        dw  irq_trap
5350 
    endif
5351 
 

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