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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [sw/] [table_tim1/] [table_tim1.asm] - Blame information for rev 131

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       cpu 6502
           output HEX
 
 
        * = $c000  ; assemble at $ff00
               code
 
 
.str_1          ASC    "Mem  " ;
                DB   $00                ;
 
 
        * = $c010  ; assemble at $ff10
 
.top       db $0a,$0d ;
           ASC    "MIK";
 
 
        * = $c0fa  ; vectors
 
          dw $0000
          dw $0000
          dw $0000
 
 code
 
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
3			`cpu 6502`
4			`output HEX`
5
6
7			`* = $c000 ; assemble at $ff00`
8			`code`
9
10
11			`.str_1 ASC "Mem " ;`
12			`DB $00 ;`
13
14
15			`* = $c010 ; assemble at $ff10`
16
17			`.top db $0a,$0d ;`
18			`ASC "MIK";`
19
20
21			`* = $c0fa ; vectors`
22
23			`dw $0000`
24			`dw $0000`
25			`dw $0000`
26
27			`code`
28
29
30
31
32
33

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [sw/] [table_tim1/] [table_tim1.asm] - Blame information for rev 131