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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [doc/] [sym/] [adv_dbg_if_wb_cpu2_jsp.sym] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
2 
B 300 0  4000 6100 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 400 6250   5 10 1 1 0 0 1 1
4 
device=adv_dbg_if_wb_cpu2_jsp
5 
T 400 6450 5 10 1 1 0 0 1 1
6 
refdes=U?
7 
T 400 6600    0 10 0 1 0 0 1 1
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vendor=opencores.org
9 
T 400 6600    0 10 0 1 0 0 1 1
10 
library=adv_debug_sys
11 
T 400 6600    0 10 0 1 0 0 1 1
12 
component=adv_dbg_if
13 
T 400 6600    0 10 0 1 0 0 1 1
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version=wb_cpu2_jsp
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P 300 200 0 200 10 1 1
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{
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T 400 200 5 10 1 1 0 1 1 1
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pinnumber=wb_jsp_sel_i[3:0]
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pinseq=1
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}
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P 300 400 0 400 10 1 1
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{
24 
T 400 400 5 10 1 1 0 1 1 1
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pinnumber=wb_jsp_dat_i[31:0]
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T 400 400 5 10 0 1 0 1 1 1
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pinseq=2
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}
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P 300 600 0 600 10 1 1
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{
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T 400 600 5 10 1 1 0 1 1 1
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pinnumber=wb_jsp_cti_i[2:0]
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pinseq=3
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}
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P 300 800 0 800 10 1 1
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{
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T 400 800 5 10 1 1 0 1 1 1
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pinnumber=wb_jsp_bte_i[1:0]
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pinseq=4
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}
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P 300 1000 0 1000 10 1 1
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{
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T 400 1000 5 10 1 1 0 1 1 1
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pinnumber=wb_jsp_adr_i[31:0]
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pinseq=5
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}
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P 300 1200 0 1200 10 1 1
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{
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T 400 1200 5 10 1 1 0 1 1 1
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pinnumber=wb_dat_i[31:0]
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T 400 1200 5 10 0 1 0 1 1 1
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pinseq=6
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}
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P 300 1400 0 1400 10 1 1
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{
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T 400 1400 5 10 1 1 0 1 1 1
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pinnumber=cpu1_data_i[31:0]
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T 400 1400 5 10 0 1 0 1 1 1
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pinseq=7
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}
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P 300 1600 0 1600 10 1 1
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{
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T 400 1600 5 10 1 1 0 1 1 1
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pinnumber=cpu0_data_i[31:0]
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T 400 1600 5 10 0 1 0 1 1 1
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pinseq=8
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}
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P 300 1800 0 1800 4 0 1
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{
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T 400 1800 5 10 1 1 0 1 1 1
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pinnumber=wb_rst_i
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T 400 1800 5 10 0 1 0 1 1 1
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pinseq=9
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P 300 2000 0 2000 4 0 1
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{
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T 400 2000 5 10 1 1 0 1 1 1
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pinnumber=wb_jsp_we_i
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pinseq=10
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}
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P 300 2200 0 2200 4 0 1
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{
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T 400 2200 5 10 1 1 0 1 1 1
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pinnumber=wb_jsp_stb_i
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pinseq=11
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}
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P 300 2400 0 2400 4 0 1
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{
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T 400 2400 5 10 1 1 0 1 1 1
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pinnumber=wb_jsp_cyc_i
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T 400 2400 5 10 0 1 0 1 1 1
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pinseq=12
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}
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P 300 2600 0 2600 4 0 1
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{
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T 400 2600 5 10 1 1 0 1 1 1
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pinnumber=wb_jsp_cab_i
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pinseq=13
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}
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P 300 2800 0 2800 4 0 1
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{
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pinnumber=wb_err_i
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T 400 2800 5 10 0 1 0 1 1 1
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pinseq=14
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}
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P 300 3000 0 3000 4 0 1
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{
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T 400 3000 5 10 1 1 0 1 1 1
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pinnumber=wb_clk_i
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T 400 3000 5 10 0 1 0 1 1 1
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pinseq=15
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P 300 3200 0 3200 4 0 1
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{
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T 400 3200 5 10 1 1 0 1 1 1
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pinnumber=wb_ack_i
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{
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T 400 3400 5 10 1 1 0 1 1 1
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pinnumber=update_dr_i
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pinseq=17
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}
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{
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T 400 3600 5 10 1 1 0 1 1 1
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pinnumber=tdi_i
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pinseq=18
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{
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P 300 4000 0 4000 4 0 1
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{
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T 400 4000 5 10 1 1 0 1 1 1
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P 300 4200 0 4200 4 0 1
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{
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T 400 4200 5 10 1 1 0 1 1 1
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{
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T 400 4400 5 10 1 1 0 1 1 1
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P 300 4600 0 4600 4 0 1
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{
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T 400 4600 5 10 1 1 0 1 1 1
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P 300 4800 0 4800 4 0 1
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{
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T 400 4800 5 10 1 1 0 1 1 1
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pinnumber=cpu1_bp_i
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T 400 4800 5 10 0 1 0 1 1 1
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pinseq=24
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P 300 5000 0 5000 4 0 1
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{
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T 400 5000 5 10 1 1 0 1 1 1
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pinnumber=cpu1_ack_i
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T 400 5000 5 10 0 1 0 1 1 1
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pinseq=25
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}
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P 300 5200 0 5200 4 0 1
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{
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T 400 5200 5 10 1 1 0 1 1 1
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pinnumber=cpu0_clk_i
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T 400 5200 5 10 0 1 0 1 1 1
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pinseq=26
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}
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P 300 5400 0 5400 4 0 1
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{
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T 400 5400 5 10 1 1 0 1 1 1
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pinnumber=cpu0_bp_i
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T 400 5400 5 10 0 1 0 1 1 1
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pinseq=27
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}
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P 300 5600 0 5600 4 0 1
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{
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T 400 5600 5 10 1 1 0 1 1 1
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pinnumber=cpu0_ack_i
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T 400 5600 5 10 0 1 0 1 1 1
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pinseq=28
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}
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P 300 5800 0 5800 4 0 1
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{
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T 400 5800 5 10 1 1 0 1 1 1
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pinnumber=capture_dr_i
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T 400 5800 5 10 0 1 0 1 1 1
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pinseq=29
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}
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P 4300 200 4600 200 10 1 1
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{
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T 4200 200 5  10 1 1 0 7 1 1
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pinnumber=wb_sel_o[3:0]
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T 4200 200 5  10 0 1 0 7 1 1
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pinseq=30
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}
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P 4300 400 4600 400 10 1 1
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{
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T 4200 400 5  10 1 1 0 7 1 1
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pinnumber=wb_jsp_dat_o[31:0]
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T 4200 400 5  10 0 1 0 7 1 1
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pinseq=31
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P 4300 600 4600 600 10 1 1
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{
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T 4200 600 5  10 1 1 0 7 1 1
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pinnumber=wb_dat_o[31:0]
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T 4200 600 5  10 0 1 0 7 1 1
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pinseq=32
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}
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P 4300 800 4600 800 10 1 1
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{
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T 4200 800 5  10 1 1 0 7 1 1
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pinnumber=wb_cti_o[2:0]
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T 4200 800 5  10 0 1 0 7 1 1
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pinseq=33
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}
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P 4300 1000 4600 1000 10 1 1
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{
248 
T 4200 1000 5  10 1 1 0 7 1 1
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pinnumber=wb_bte_o[1:0]
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T 4200 1000 5  10 0 1 0 7 1 1
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pinseq=34
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P 4300 1200 4600 1200 10 1 1
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{
255 
T 4200 1200 5  10 1 1 0 7 1 1
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pinnumber=wb_adr_o[31:0]
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T 4200 1200 5  10 0 1 0 7 1 1
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pinseq=35
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}
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P 4300 1400 4600 1400 10 1 1
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{
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T 4200 1400 5  10 1 1 0 7 1 1
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pinnumber=cpu1_data_o[31:0]
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T 4200 1400 5  10 0 1 0 7 1 1
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pinseq=36
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}
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P 4300 1600 4600 1600 10 1 1
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{
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T 4200 1600 5  10 1 1 0 7 1 1
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pinnumber=cpu1_addr_o[31:0]
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T 4200 1600 5  10 0 1 0 7 1 1
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pinseq=37
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}
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P 4300 1800 4600 1800 10 1 1
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{
276 
T 4200 1800 5  10 1 1 0 7 1 1
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pinnumber=cpu0_data_o[31:0]
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T 4200 1800 5  10 0 1 0 7 1 1
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pinseq=38
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}
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P 4300 2000 4600 2000 10 1 1
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{
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T 4200 2000 5  10 1 1 0 7 1 1
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pinnumber=cpu0_addr_o[31:0]
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T 4200 2000 5  10 0 1 0 7 1 1
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pinseq=39
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}
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P 4300 2200 4600 2200 4 0 1
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{
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T 4200 2200 5  10 1 1 0 7 1 1
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T 4300 2200 5  10 0 1 0 7 1 1
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pinseq=40
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}
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P 4300 2400 4600 2400 4 0 1
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{
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T 4200 2400 5  10 1 1 0 7 1 1
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T 4300 2400 5  10 0 1 0 7 1 1
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pinseq=41
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}
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P 4300 2600 4600 2600 4 0 1
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{
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T 4200 2600 5  10 1 1 0 7 1 1
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T 4300 2600 5  10 0 1 0 7 1 1
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pinseq=42
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}
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P 4300 2800 4600 2800 4 0 1
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{
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T 4200 2800 5  10 1 1 0 7 1 1
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pinseq=43
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P 4300 3000 4600 3000 4 0 1
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{
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T 4200 3000 5  10 1 1 0 7 1 1
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T 4300 3000 5  10 0 1 0 7 1 1
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pinseq=44
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P 4300 3200 4600 3200 4 0 1
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{
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T 4200 3200 5  10 1 1 0 7 1 1
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T 4300 3200 5  10 0 1 0 7 1 1
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pinseq=45
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P 4300 3400 4600 3400 4 0 1
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{
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T 4200 3400 5  10 1 1 0 7 1 1
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pinseq=46
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{
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T 4200 3600 5  10 1 1 0 7 1 1
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pinseq=47
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P 4300 3800 4600 3800 4 0 1
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{
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T 4200 3800 5  10 1 1 0 7 1 1
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pinnumber=cpu1_we_o
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pinseq=48
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P 4300 4000 4600 4000 4 0 1
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{
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T 4200 4000 5  10 1 1 0 7 1 1
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pinseq=49
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P 4300 4200 4600 4200 4 0 1
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{
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pinseq=50
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P 4300 4400 4600 4400 4 0 1
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{
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T 4200 4400 5  10 1 1 0 7 1 1
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pinseq=51
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P 4300 4600 4600 4600 4 0 1
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{
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T 4200 4600 5  10 1 1 0 7 1 1
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pinseq=52
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P 4300 4800 4600 4800 4 0 1
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{
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T 4200 4800 5  10 1 1 0 7 1 1
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pinseq=53
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}
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P 4300 5000 4600 5000 4 0 1
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{
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T 4200 5000 5  10 1 1 0 7 1 1
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pinseq=54
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}
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P 4300 5200 4600 5200 4 0 1
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{
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T 4200 5200 5  10 1 1 0 7 1 1
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pinnumber=cpu0_rst_o
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T 4300 5200 5  10 0 1 0 7 1 1
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pinseq=55
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}

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