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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  adbg_jfifo_biu.v                                              ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC Debug Interface.               ////
////                                                              ////
////  Author(s):                                                  ////
////       Nathan Yawn (nathan.yawn@opencores.org)                ////
////                                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2010        Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// This is where the magic happens in the JTAG Serial Port.  The serial
// port FIFOs and counters are kept in the WishBone clock domain.
// 'Syncflop' elements are used to synchronize strobe lines across
// clock domains, and 'syncreg' elements keep the byte and free count
// as current as possible in the JTAG clock domain.  Also in the WB
// clock domain is a WishBone target interface, which more or less
// tries to emulate a 16550 without FIFOs (despite the fact that
// FIFOs are actually present, they are opaque to the WB interface.)
//
 
 
// Top module
module `VARIANT`JFIFO_BIU
  (
   // Debug interface signals
   tck_i,
   rst_i,
   data_o,
   bytes_available_o,
   bytes_free_o,
   rd_strobe_i,
   wr_strobe_i,
 
   // Wishbone signals
   wb_clk_i,
   wb_dat_i,
   wb_stb_i
   );
 
   // Debug interface signals
   input tck_i;
   input rst_i;
   output [7:0] data_o;
   output [3:0] bytes_free_o;
   output [3:0] bytes_available_o;
   input        rd_strobe_i;
   input        wr_strobe_i;
 
   // Wishbone signals
   input         wb_clk_i;
   input  [7:0]  wb_dat_i;
   input         wb_stb_i;
 
 
 
   wire [7:0]     data_o;
   wire [3:0]     bytes_free_o;
   assign        bytes_free_o = 4'b0100;
 
   wire [3:0]     bytes_available_o;
 
   // Registers
 
   reg [7:0]      rdata;
   reg           ren_tff;
 
   // Wires  
   wire          wb_fifo_ack;
   wire [3:0]     wr_bytes_free;
   wire [3:0]     rd_bytes_avail;
   wire [3:0]     wr_bytes_avail;  // used to generate wr_fifo_not_empty
   assign       wr_bytes_avail = 4'b0000;
 
 
   wire          rd_bytes_avail_not_zero;
   wire          ren_sff_out;
   wire [7:0]     rd_fifo_data_out;
 
   wire          wr_fifo_not_empty;  // this is for the WishBone interface LSR register
 
   // Control Signals (FSM outputs)
 
   reg           ren_rst;   // reset 'pop' SFF
   reg           rdata_en;  // enable 'rdata' register
   reg           rpp;       // read FIFO PUSH (1) or POP (0)
   reg           r_fifo_en; // enable read FIFO    
   reg           r_wb_ack;  // read FSM acks WB transaction
 
 
   // Indicators to FSMs
 
   wire          pop;         // JTAG side received a byte, pop and get next
   wire          rcz;         // zero bytes available in read FIFO
 
 
 
   //////////////////////////////////////////////////////
   // TCK clock domain
   // There is no FSM here, just signal latching and clock
   // domain synchronization
 
   assign        data_o = rdata;
 
 
   // Read enable (REN) toggle FF
   always @ (posedge tck_i or posedge rst_i)
     begin
        if(rst_i) ren_tff <= 1'b0;
        else if(rd_strobe_i) ren_tff <= ~ren_tff;
     end
 
 
 
 
   ///////////////////////////////////////////////////////
   // Wishbone clock domain
 
   // Combinatorial assignments
   assign rd_bytes_avail_not_zero = !(rd_bytes_avail == 4'h0);
   assign pop = ren_sff_out & rd_bytes_avail_not_zero;
   assign rcz = ~rd_bytes_avail_not_zero;
   assign wb_fifo_ack = r_wb_ack ;
   assign wr_fifo_not_empty = 1'b0;
 
   // rdata register
   always @ (posedge wb_clk_i or posedge rst_i)
     begin
        if(rst_i) rdata <= 8'h0;
        else if(rdata_en) rdata <= rd_fifo_data_out;
     end
 
 
   // REN SFF
   `VARIANT`SYNCFLOP ren_sff (
                     .DEST_CLK(wb_clk_i),
                     .D_SET(1'b0),
                     .D_RST(ren_rst),
                     .RESET(rst_i),
                     .TOGGLE_IN(ren_tff),
                     .D_OUT(ren_sff_out)
                     );
 
 
 
   // 'bytes available' syncreg
   `VARIANT`SYNCREG bytesavail_syncreg (
                              .CLKA(wb_clk_i),
                              .CLKB(tck_i),
                              .RST(rst_i),
                              .DATA_IN(rd_bytes_avail),
                              .DATA_OUT(bytes_available_o)
                              );
 
 
   // read FIFO
   `VARIANT`BYTEFIFO rd_fifo (
                     .CLK          ( wb_clk_i          ),
                     .RST          ( rst_i             ),  // rst_i from JTAG clk domain, xmit_fifo_rst from WB, RST is async reset
                     .DATA_IN      ( wb_dat_i[7:0]     ),
                     .DATA_OUT     ( rd_fifo_data_out  ),
                     .PUSH_POPn    ( rpp               ),
                     .EN           ( r_fifo_en         ),
                     .BYTES_AVAIL  ( rd_bytes_avail    ),
                     .BYTES_FREE   (                   )
                     );
 
 
 
 
 
   /////////////////////////////////////////////////////
   // State machine for the read FIFO
 
   reg [1:0] rd_fsm_state;
   reg [1:0]   next_rd_fsm_state;
 
`define STATE_RD_IDLE     2'h0
`define STATE_RD_PUSH     2'h1
`define STATE_RD_POP      2'h2
`define STATE_RD_LATCH    2'h3
 
   // Sequential bit
   always @ (posedge wb_clk_i or posedge rst_i)
     begin
        if(rst_i) rd_fsm_state <= `STATE_RD_IDLE;
        else rd_fsm_state <= next_rd_fsm_state;
     end
 
   // Determination of next state (combinatorial)
   always @ (*)
     begin
        case (rd_fsm_state)
          `STATE_RD_IDLE:
            begin
               if(wb_stb_i) next_rd_fsm_state = `STATE_RD_PUSH;
               else if (pop) next_rd_fsm_state = `STATE_RD_POP;
               else next_rd_fsm_state = `STATE_RD_IDLE;
            end
          `STATE_RD_PUSH:
            begin
               if(rcz) next_rd_fsm_state = `STATE_RD_LATCH;  // putting first item in fifo, move to rdata in state LATCH
               else if(pop) next_rd_fsm_state = `STATE_RD_POP;
               else next_rd_fsm_state = `STATE_RD_IDLE;
            end
          `STATE_RD_POP:
            begin
               next_rd_fsm_state = `STATE_RD_LATCH; // new data at FIFO head, move to rdata in state LATCH
            end
          `STATE_RD_LATCH:
            begin
               if(wb_stb_i) next_rd_fsm_state = `STATE_RD_PUSH;
               else if(pop) next_rd_fsm_state = `STATE_RD_POP;
               else next_rd_fsm_state = `STATE_RD_IDLE;
            end
          default:
            begin
               next_rd_fsm_state = `STATE_RD_IDLE;
            end
        endcase
     end
 
   // Outputs of state machine (combinatorial)
   always @ (rd_fsm_state)
     begin
        ren_rst = 1'b0;
        rpp = 1'b0;
        r_fifo_en = 1'b0;
        rdata_en = 1'b0;
        r_wb_ack = 1'b0;
 
        case (rd_fsm_state)
          `STATE_RD_IDLE:;
 
          `STATE_RD_PUSH:
            begin
               rpp = 1'b1;
               r_fifo_en = 1'b1;
               r_wb_ack = 1'b1;
            end
 
          `STATE_RD_POP:
            begin
               ren_rst = 1'b1;
               r_fifo_en = 1'b1;
            end
 
          `STATE_RD_LATCH:
            begin
               rdata_en = 1'b1;
            end
        endcase
     end
 
 
 
 
 
 
 
 
 
 
 
 
 
 
endmodule
 

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [verilog/] [adbg_jfifo_biu.v] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// adbg_jfifo_biu.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC Debug Interface. ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// Nathan Yawn (nathan.yawn@opencores.org) ////`
10			`//// ////`
11			`//// ////`
12			`//// ////`
13			`//////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2010 Authors ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer. ////`
21			`//// ////`
22			`//// This source file is free software; you can redistribute it ////`
23			`//// and/or modify it under the terms of the GNU Lesser General ////`
24			`//// Public License as published by the Free Software Foundation; ////`
25			`//// either version 2.1 of the License, or (at your option) any ////`
26			`//// later version. ////`
27			`//// ////`
28			`//// This source is distributed in the hope that it will be ////`
29			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
30			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
31			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
32			`//// details. ////`
33			`//// ////`
34			`//// You should have received a copy of the GNU Lesser General ////`
35			`//// Public License along with this source; if not, download it ////`
36			`//// from http://www.opencores.org/lgpl.shtml ////`
37			`//// ////`
38			`//////////////////////////////////////////////////////////////////////`
39			`//`
40			`// This is where the magic happens in the JTAG Serial Port. The serial`
41			`// port FIFOs and counters are kept in the WishBone clock domain.`
42			`// 'Syncflop' elements are used to synchronize strobe lines across`
43			`// clock domains, and 'syncreg' elements keep the byte and free count`
44			`// as current as possible in the JTAG clock domain. Also in the WB`
45			`// clock domain is a WishBone target interface, which more or less`
46			`// tries to emulate a 16550 without FIFOs (despite the fact that`
47			`// FIFOs are actually present, they are opaque to the WB interface.)`
48			`//`
49
50
51			`// Top module`
52			module `VARIANT`JFIFO_BIU
53			`(`
54			`// Debug interface signals`
55			`tck_i,`
56			`rst_i,`
57			`data_o,`
58			`bytes_available_o,`
59			`bytes_free_o,`
60			`rd_strobe_i,`
61			`wr_strobe_i,`
62
63			`// Wishbone signals`
64			`wb_clk_i,`
65			`wb_dat_i,`
66			`wb_stb_i`
67			`);`
68
69			`// Debug interface signals`
70			`input tck_i;`
71			`input rst_i;`
72			`output [7:0] data_o;`
73			`output [3:0] bytes_free_o;`
74			`output [3:0] bytes_available_o;`
75			`input rd_strobe_i;`
76			`input wr_strobe_i;`
77
78			`// Wishbone signals`
79			`input wb_clk_i;`
80			`input [7:0] wb_dat_i;`
81			`input wb_stb_i;`
82
83
84
85			`wire [7:0] data_o;`
86			`wire [3:0] bytes_free_o;`
87			`assign bytes_free_o = 4'b0100;`
88
89			`wire [3:0] bytes_available_o;`
90
91			`// Registers`
92
93			`reg [7:0] rdata;`
94			`reg ren_tff;`
95
96			`// Wires`
97			`wire wb_fifo_ack;`
98			`wire [3:0] wr_bytes_free;`
99			`wire [3:0] rd_bytes_avail;`
100			`wire [3:0] wr_bytes_avail; // used to generate wr_fifo_not_empty`
101			`assign wr_bytes_avail = 4'b0000;`
102
103
104			`wire rd_bytes_avail_not_zero;`
105			`wire ren_sff_out;`
106			`wire [7:0] rd_fifo_data_out;`
107
108			`wire wr_fifo_not_empty; // this is for the WishBone interface LSR register`
109
110			`// Control Signals (FSM outputs)`
111
112			`reg ren_rst; // reset 'pop' SFF`
113			`reg rdata_en; // enable 'rdata' register`
114			`reg rpp; // read FIFO PUSH (1) or POP (0)`
115			`reg r_fifo_en; // enable read FIFO`
116			`reg r_wb_ack; // read FSM acks WB transaction`
117
118
119			`// Indicators to FSMs`
120
121			`wire pop; // JTAG side received a byte, pop and get next`
122			`wire rcz; // zero bytes available in read FIFO`
123
124
125
126			`//////////////////////////////////////////////////////`
127			`// TCK clock domain`
128			`// There is no FSM here, just signal latching and clock`
129			`// domain synchronization`
130
131			`assign data_o = rdata;`
132
133
134			`// Read enable (REN) toggle FF`
135			`always @ (posedge tck_i or posedge rst_i)`
136			`begin`
137			`if(rst_i) ren_tff <= 1'b0;`
138			`else if(rd_strobe_i) ren_tff <= ~ren_tff;`
139			`end`
140
141
142
143
144			`///////////////////////////////////////////////////////`
145			`// Wishbone clock domain`
146
147			`// Combinatorial assignments`
148			`assign rd_bytes_avail_not_zero = !(rd_bytes_avail == 4'h0);`
149			`assign pop = ren_sff_out & rd_bytes_avail_not_zero;`
150			`assign rcz = ~rd_bytes_avail_not_zero;`
151			`assign wb_fifo_ack = r_wb_ack ;`
152			`assign wr_fifo_not_empty = 1'b0;`
153
154			`// rdata register`
155			`always @ (posedge wb_clk_i or posedge rst_i)`
156			`begin`
157			`if(rst_i) rdata <= 8'h0;`
158			`else if(rdata_en) rdata <= rd_fifo_data_out;`
159			`end`
160
161
162			`// REN SFF`
163			`VARIANT`SYNCFLOP ren_sff (
164			`.DEST_CLK(wb_clk_i),`
165			`.D_SET(1'b0),`
166			`.D_RST(ren_rst),`
167			`.RESET(rst_i),`
168			`.TOGGLE_IN(ren_tff),`
169			`.D_OUT(ren_sff_out)`
170			`);`
171
172
173
174			`// 'bytes available' syncreg`
175			`VARIANT`SYNCREG bytesavail_syncreg (
176			`.CLKA(wb_clk_i),`
177			`.CLKB(tck_i),`
178			`.RST(rst_i),`
179			`.DATA_IN(rd_bytes_avail),`
180			`.DATA_OUT(bytes_available_o)`
181			`);`
182
183
184			`// read FIFO`
185			`VARIANT`BYTEFIFO rd_fifo (
186			`.CLK ( wb_clk_i ),`
187			`.RST ( rst_i ), // rst_i from JTAG clk domain, xmit_fifo_rst from WB, RST is async reset`
188			`.DATA_IN ( wb_dat_i[7:0] ),`
189			`.DATA_OUT ( rd_fifo_data_out ),`
190			`.PUSH_POPn ( rpp ),`
191			`.EN ( r_fifo_en ),`
192			`.BYTES_AVAIL ( rd_bytes_avail ),`
193			`.BYTES_FREE ( )`
194			`);`
195
196
197
198
199
200			`/////////////////////////////////////////////////////`
201			`// State machine for the read FIFO`
202
203			`reg [1:0] rd_fsm_state;`
204			`reg [1:0] next_rd_fsm_state;`
205
206			`define STATE_RD_IDLE 2'h0
207			`define STATE_RD_PUSH 2'h1
208			`define STATE_RD_POP 2'h2
209			`define STATE_RD_LATCH 2'h3
210
211			`// Sequential bit`
212			`always @ (posedge wb_clk_i or posedge rst_i)`
213			`begin`
214			if(rst_i) rd_fsm_state <= `STATE_RD_IDLE;
215			`else rd_fsm_state <= next_rd_fsm_state;`
216			`end`
217
218			`// Determination of next state (combinatorial)`
219			`always @ (*)`
220			`begin`
221			`case (rd_fsm_state)`
222			`STATE_RD_IDLE:
223			`begin`
224			if(wb_stb_i) next_rd_fsm_state = `STATE_RD_PUSH;
225			else if (pop) next_rd_fsm_state = `STATE_RD_POP;
226			else next_rd_fsm_state = `STATE_RD_IDLE;
227			`end`
228			`STATE_RD_PUSH:
229			`begin`
230			if(rcz) next_rd_fsm_state = `STATE_RD_LATCH; // putting first item in fifo, move to rdata in state LATCH
231			else if(pop) next_rd_fsm_state = `STATE_RD_POP;
232			else next_rd_fsm_state = `STATE_RD_IDLE;
233			`end`
234			`STATE_RD_POP:
235			`begin`
236			next_rd_fsm_state = `STATE_RD_LATCH; // new data at FIFO head, move to rdata in state LATCH
237			`end`
238			`STATE_RD_LATCH:
239			`begin`
240			if(wb_stb_i) next_rd_fsm_state = `STATE_RD_PUSH;
241			else if(pop) next_rd_fsm_state = `STATE_RD_POP;
242			else next_rd_fsm_state = `STATE_RD_IDLE;
243			`end`
244			`default:`
245			`begin`
246			next_rd_fsm_state = `STATE_RD_IDLE;
247			`end`
248			`endcase`
249			`end`
250
251			`// Outputs of state machine (combinatorial)`
252			`always @ (rd_fsm_state)`
253			`begin`
254			`ren_rst = 1'b0;`
255			`rpp = 1'b0;`
256			`r_fifo_en = 1'b0;`
257			`rdata_en = 1'b0;`
258			`r_wb_ack = 1'b0;`
259
260			`case (rd_fsm_state)`
261			`STATE_RD_IDLE:;
262
263			`STATE_RD_PUSH:
264			`begin`
265			`rpp = 1'b1;`
266			`r_fifo_en = 1'b1;`
267			`r_wb_ack = 1'b1;`
268			`end`
269
270			`STATE_RD_POP:
271			`begin`
272			`ren_rst = 1'b1;`
273			`r_fifo_en = 1'b1;`
274			`end`
275
276			`STATE_RD_LATCH:
277			`begin`
278			`rdata_en = 1'b1;`
279			`end`
280			`endcase`
281			`end`
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296			`endmodule`
297