URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [verilog/] [adbg_wb_cpu0_jfifo.v] - Blame information for rev 131

Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  adbg_top.v                                                  ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC Advanced Debug Interface.      ////
////                                                              ////
////  Author(s):                                                  ////
////       Nathan Yawn (nathan.yawn@opencores.org)                ////
////                                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2008-2010 Authors                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
 
 
 
 
// Top module
module `VARIANT (
                // JTAG signals
                tck_i,
                tdi_i,
                tdo_o,
                rst_i,
 
 
                // TAP states
                shift_dr_i,
                update_dr_i,
                capture_dr_i,
 
                // Instructions
                debug_select_i
 
 
                `ifdef DBG_WISHBONE_SUPPORTED
                // WISHBONE common signals
                ,
                wb_clk_i,
                wb_rst_i,
 
                // WISHBONE master interface
                wb_adr_o,
                wb_dat_o,
                wb_dat_i,
                wb_cyc_o,
                wb_stb_o,
                wb_sel_o,
                wb_we_o,
                wb_ack_i,
                wb_cab_o,
                wb_err_i,
                wb_cti_o,
                wb_bte_o
                `endif
 
                `ifdef DBG_CPU0_SUPPORTED
                // CPU signals
                ,
                cpu0_clk_i,
                cpu0_addr_o,
                cpu0_data_i,
                cpu0_data_o,
                cpu0_bp_i,
                cpu0_stall_o,
                cpu0_stb_o,
                cpu0_we_o,
                cpu0_ack_i,
                cpu0_rst_o
                `endif
 
                `ifdef DBG_CPU1_SUPPORTED
                // CPU signals
                ,
                cpu1_clk_i,
                cpu1_addr_o,
                cpu1_data_i,
                cpu1_data_o,
                cpu1_bp_i,
                cpu1_stall_o,
                cpu1_stb_o,
                cpu1_we_o,
                cpu1_ack_i,
                cpu1_rst_o
                `endif
 
                `ifdef DBG_JSP_SUPPORTED
                ,
                `ifndef DBG_WISHBONE_SUPPORTED
                wb_clk_i,
                `endif
 
                // WISHBONE target interface
                wb_jsp_dat_i,
                wb_jsp_stb_i,
                biu_wr_strobe,
                jsp_data_out
                `endif
 
                );
 
 
   // JTAG signals
   input   tck_i;
   input   tdi_i;
   output  tdo_o;
   input   rst_i;
 
   // TAP states
   input   shift_dr_i;
   input   update_dr_i;
   input   capture_dr_i;
 
   // Module select from TAP
   input   debug_select_i;
 
`ifdef DBG_WISHBONE_SUPPORTED
   input   wb_clk_i;
   input   wb_rst_i;
   output [31:0] wb_adr_o;
   output [31:0] wb_dat_o;
   input [31:0]  wb_dat_i;
   output        wb_cyc_o;
   output        wb_stb_o;
   output [3:0]  wb_sel_o;
   output        wb_we_o;
   input         wb_ack_i;
   output        wb_cab_o;
   input         wb_err_i;
   output [2:0]  wb_cti_o;
   output [1:0]  wb_bte_o;
`endif
 
`ifdef DBG_CPU0_SUPPORTED
   // CPU signals
   input         cpu0_clk_i;
   output [31:0] cpu0_addr_o;
   input [31:0]  cpu0_data_i;
   output [31:0] cpu0_data_o;
   input         cpu0_bp_i;
   output        cpu0_stall_o;
   output        cpu0_stb_o;
   output        cpu0_we_o;
   input         cpu0_ack_i;
   output        cpu0_rst_o;
`endif
 
`ifdef DBG_CPU1_SUPPORTED
   input         cpu1_clk_i;
   output [31:0] cpu1_addr_o;
   input [31:0]  cpu1_data_i;
   output [31:0] cpu1_data_o;
   input         cpu1_bp_i;
   output        cpu1_stall_o;
   output        cpu1_stb_o;
   output        cpu1_we_o;
   input         cpu1_ack_i;
   output        cpu1_rst_o;
`endif
 
`ifdef DBG_JSP_SUPPORTED
   `ifndef DBG_WISHBONE_SUPPORTED
   input   wb_clk_i;
   `endif
   input [7:0]   wb_jsp_dat_i;
   input         wb_jsp_stb_i;
   output        biu_wr_strobe;
   output [7:0]   jsp_data_out;
`endif
 
   reg           tdo_o;
   wire          tdo_wb;
   wire          tdo_cpu0;
   wire          tdo_cpu1;
   wire          tdo_jsp;
 
   // Registers
   reg [`DBG_TOP_MODULE_DATA_LEN-1:0] input_shift_reg;  // 1 bit sel/cmd, 4 bit opcode, 32 bit address, 16 bit length = 53 bits
   //reg output_shift_reg;  // Just 1 bit for status (valid module selected)
   reg [`DBG_TOP_MODULE_ID_LENGTH -1:0] module_id_reg;   // Module selection register
 
 
   // Control signals
   wire                                 select_cmd;  // True when the command (registered at Update_DR) is for top level/module selection
   wire [(`DBG_TOP_MODULE_ID_LENGTH - 1) : 0] module_id_in;    // The part of the input_shift_register to be used as the module select data
   reg [(`DBG_TOP_MAX_MODULES - 1) : 0]       module_selects;  // Select signals for the individual modules
   wire                                       select_inhibit;  // OR of inhibit signals from sub-modules, prevents latching of a new module ID
   wire [3:0]                                  module_inhibit;  // signals to allow submodules to prevent top level from latching new module ID
 
   ///////////////////////////////////////
   // Combinatorial assignments
 
assign select_cmd = input_shift_reg[52];
assign module_id_in = input_shift_reg[51:50];
 
//////////////////////////////////////////////////////////
// Module select register and select signals
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    module_id_reg <= 2'b0;
  else if(debug_select_i && select_cmd && update_dr_i && !select_inhibit)       // Chain select
    module_id_reg <= module_id_in;
end
 
 
always @ (module_id_reg)
begin
        module_selects                 = `DBG_TOP_MODULE_ID_LENGTH'h0;
        module_selects[module_id_reg]  = 1'b1;
end
 
///////////////////////////////////////////////
// Data input shift register
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    input_shift_reg <= 53'h0;
  else if(debug_select_i && shift_dr_i)
    input_shift_reg <= {tdi_i, input_shift_reg[52:1]};
end
 
 
//////////////////////////////////////////////
// Debug module instantiations
 
`ifdef DBG_WISHBONE_SUPPORTED
// Connecting wishbone module
`VARIANT`WB_MODULE i_dbg_wb (
                  // JTAG signals
                  .tck_i            (tck_i),
                  .module_tdo_o     (tdo_wb),
                  .tdi_i            (tdi_i),
 
                  // TAP states
                  .capture_dr_i     (capture_dr_i),
                  .shift_dr_i       (shift_dr_i),
                  .update_dr_i      (update_dr_i),
 
                  .data_register_i  (input_shift_reg),
                  .module_select_i  (module_selects[`DBG_TOP_WISHBONE_DEBUG_MODULE]),
                  .top_inhibit_o     (module_inhibit[`DBG_TOP_WISHBONE_DEBUG_MODULE]),
                  .rst_i            (rst_i),
 
                  // WISHBONE common signals
                  .wb_clk_i         (wb_clk_i),
 
                  // WISHBONE master interface
                  .wb_adr_o         (wb_adr_o),
                  .wb_dat_o         (wb_dat_o),
                  .wb_dat_i         (wb_dat_i),
                  .wb_cyc_o         (wb_cyc_o),
                  .wb_stb_o         (wb_stb_o),
                  .wb_sel_o         (wb_sel_o),
                  .wb_we_o          (wb_we_o),
                  .wb_ack_i         (wb_ack_i),
                  .wb_cab_o         (wb_cab_o),
                  .wb_err_i         (wb_err_i),
                  .wb_cti_o         (wb_cti_o),
                  .wb_bte_o         (wb_bte_o)
            );
`else
assign tdo_wb = 1'b0;
assign module_inhibit[`DBG_TOP_WISHBONE_DEBUG_MODULE] = 1'b0;
`endif
 
 
 
`ifdef DBG_CPU0_SUPPORTED
`VARIANT`OR1K_MODULE i_dbg_cpu_or1k (
                  // JTAG signals
                  .tck_i            (tck_i),
                  .module_tdo_o     (tdo_cpu0),
                  .tdi_i            (tdi_i),
 
                  // TAP states
                  .capture_dr_i     (capture_dr_i),
                  .shift_dr_i       (shift_dr_i),
                  .update_dr_i      (update_dr_i),
 
                  .data_register_i  (input_shift_reg),
                  .module_select_i  (module_selects[`DBG_TOP_CPU0_DEBUG_MODULE]),
                  .top_inhibit_o     (module_inhibit[`DBG_TOP_CPU0_DEBUG_MODULE]),
                  .rst_i            (rst_i),
 
                  // CPU signals
                  .cpu_clk_i        (cpu0_clk_i),
                  .cpu_addr_o       (cpu0_addr_o),
                  .cpu_data_i       (cpu0_data_i),
                  .cpu_data_o       (cpu0_data_o),
                  .cpu_bp_i         (cpu0_bp_i),
                  .cpu_stall_o      (cpu0_stall_o),
                  .cpu_stb_o        (cpu0_stb_o),
                  .cpu_we_o         (cpu0_we_o),
                  .cpu_ack_i        (cpu0_ack_i),
                  .cpu_rst_o        (cpu0_rst_o)
              );
`else
assign tdo_cpu0 = 1'b0;
assign module_inhibit[`DBG_TOP_CPU0_DEBUG_MODULE] = 1'b0;
`endif  //  DBG_CPU0_SUPPORTED
 
 
 
`ifdef DBG_CPU1_SUPPORTED
// Connecting cpu module
`VARIANT`OR1K_MODULE  i_dbg_cpu_2 (
                  // JTAG signals
                  .tck_i            (tck_i),
                  .module_tdo_o     (tdo_cpu1),
                  .tdi_i            (tdi_i),
 
                  // TAP states
                  .capture_dr_i     (capture_dr_i),
                  .shift_dr_i       (shift_dr_i),
                  .update_dr_i      (update_dr_i),
 
                  .data_register_i  (input_shift_reg),
                  .module_select_i  (module_selects[`DBG_TOP_CPU1_DEBUG_MODULE]),
                  .top_inhibit_o    (module_inhibit[`DBG_TOP_CPU1_DEBUG_MODULE]),
                  .rst_i            (rst_i),
 
                  // CPU signals
                  .cpu_clk_i        (cpu1_clk_i),
                  .cpu_addr_o       (cpu1_addr_o),
                  .cpu_data_i       (cpu1_data_i),
                  .cpu_data_o       (cpu1_data_o),
                  .cpu_bp_i         (cpu1_bp_i),
                  .cpu_stall_o      (cpu1_stall_o),
                  .cpu_stb_o        (cpu1_stb_o),
                  .cpu_we_o         (cpu1_we_o),
                  .cpu_ack_i        (cpu1_ack_i),
                  .cpu_rst_o        (cpu1_rst_o)
              );
`else
assign tdo_cpu1 = 1'b0;
assign module_inhibit[`DBG_TOP_CPU1_DEBUG_MODULE] = 1'b0;
`endif
 
`ifdef DBG_JSP_SUPPORTED
`VARIANT`JFIFO_MODULE i_dbg_jfifo (
                  // JTAG signals
                  .tck_i            (tck_i),
                  .module_tdo_o     (tdo_jsp),
                  .tdi_i            (tdi_i),
 
                  // TAP states
                  .capture_dr_i     (capture_dr_i),
                  .shift_dr_i       (shift_dr_i),
                  .update_dr_i      (update_dr_i),
 
                  .data_register_i  (input_shift_reg),
//                  .module_select_i  (module_selects[`DBG_TOP_JSP_DEBUG_MODULE]),
                  .module_select_i  (debug_select_i),
                  .rst_i            (rst_i),
 
                  // WISHBONE common signals
                  .wb_clk_i         (wb_clk_i),
 
                  // WISHBONE master interface
                  .wb_dat_i         (wb_jsp_dat_i),
                  .wb_stb_i         (wb_jsp_stb_i),
                  .biu_wr_strobe    (biu_wr_strobe),
                  .jsp_data_out     (jsp_data_out)
 
            );
 
`else
   assign tdo_jsp = 1'b0;
 
`endif
 
assign module_inhibit[`DBG_TOP_JSP_DEBUG_MODULE] = 1'b0;
 
 
assign select_inhibit = |module_inhibit;
 
/////////////////////////////////////////////////
// TDO output MUX
 
always @ (module_id_reg or tdo_wb or tdo_cpu0 or tdo_cpu1 or tdo_jsp)
begin
   case (module_id_reg)
     `DBG_TOP_WISHBONE_DEBUG_MODULE: tdo_o = tdo_wb;
     `DBG_TOP_CPU0_DEBUG_MODULE:     tdo_o = tdo_cpu0;
     `DBG_TOP_CPU1_DEBUG_MODULE:     tdo_o = tdo_cpu1;
     `DBG_TOP_JSP_DEBUG_MODULE:      tdo_o = tdo_jsp;
       default:                        tdo_o = 1'b0;
   endcase
end
 
 
endmodule

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [verilog/] [adbg_wb_cpu0_jfifo.v] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// adbg_top.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC Advanced Debug Interface. ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// Nathan Yawn (nathan.yawn@opencores.org) ////`
10			`//// ////`
11			`//// ////`
12			`//// ////`
13			`//////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2008-2010 Authors ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer. ////`
21			`//// ////`
22			`//// This source file is free software; you can redistribute it ////`
23			`//// and/or modify it under the terms of the GNU Lesser General ////`
24			`//// Public License as published by the Free Software Foundation; ////`
25			`//// either version 2.1 of the License, or (at your option) any ////`
26			`//// later version. ////`
27			`//// ////`
28			`//// This source is distributed in the hope that it will be ////`
29			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
30			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
31			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
32			`//// details. ////`
33			`//// ////`
34			`//// You should have received a copy of the GNU Lesser General ////`
35			`//// Public License along with this source; if not, download it ////`
36			`//// from http://www.opencores.org/lgpl.shtml ////`
37			`//// ////`
38			`//////////////////////////////////////////////////////////////////////`
39
40
41
42
43
44			`// Top module`
45			module `VARIANT (
46			`// JTAG signals`
47			`tck_i,`
48			`tdi_i,`
49			`tdo_o,`
50			`rst_i,`
51
52
53			`// TAP states`
54			`shift_dr_i,`
55			`update_dr_i,`
56			`capture_dr_i,`
57
58			`// Instructions`
59			`debug_select_i`
60
61
62			`ifdef DBG_WISHBONE_SUPPORTED
63			`// WISHBONE common signals`
64			`,`
65			`wb_clk_i,`
66			`wb_rst_i,`
67
68			`// WISHBONE master interface`
69			`wb_adr_o,`
70			`wb_dat_o,`
71			`wb_dat_i,`
72			`wb_cyc_o,`
73			`wb_stb_o,`
74			`wb_sel_o,`
75			`wb_we_o,`
76			`wb_ack_i,`
77			`wb_cab_o,`
78			`wb_err_i,`
79			`wb_cti_o,`
80			`wb_bte_o`
81			`endif
82
83			`ifdef DBG_CPU0_SUPPORTED
84			`// CPU signals`
85			`,`
86			`cpu0_clk_i,`
87			`cpu0_addr_o,`
88			`cpu0_data_i,`
89			`cpu0_data_o,`
90			`cpu0_bp_i,`
91			`cpu0_stall_o,`
92			`cpu0_stb_o,`
93			`cpu0_we_o,`
94			`cpu0_ack_i,`
95			`cpu0_rst_o`
96			`endif
97
98			`ifdef DBG_CPU1_SUPPORTED
99			`// CPU signals`
100			`,`
101			`cpu1_clk_i,`
102			`cpu1_addr_o,`
103			`cpu1_data_i,`
104			`cpu1_data_o,`
105			`cpu1_bp_i,`
106			`cpu1_stall_o,`
107			`cpu1_stb_o,`
108			`cpu1_we_o,`
109			`cpu1_ack_i,`
110			`cpu1_rst_o`
111			`endif
112
113			`ifdef DBG_JSP_SUPPORTED
114			`,`
115			`ifndef DBG_WISHBONE_SUPPORTED
116			`wb_clk_i,`
117			`endif
118
119			`// WISHBONE target interface`
120			`wb_jsp_dat_i,`
121			`wb_jsp_stb_i,`
122			`biu_wr_strobe,`
123			`jsp_data_out`
124			`endif
125
126			`);`
127
128
129			`// JTAG signals`
130			`input tck_i;`
131			`input tdi_i;`
132			`output tdo_o;`
133			`input rst_i;`
134
135			`// TAP states`
136			`input shift_dr_i;`
137			`input update_dr_i;`
138			`input capture_dr_i;`
139
140			`// Module select from TAP`
141			`input debug_select_i;`
142
143			`ifdef DBG_WISHBONE_SUPPORTED
144			`input wb_clk_i;`
145			`input wb_rst_i;`
146			`output [31:0] wb_adr_o;`
147			`output [31:0] wb_dat_o;`
148			`input [31:0] wb_dat_i;`
149			`output wb_cyc_o;`
150			`output wb_stb_o;`
151			`output [3:0] wb_sel_o;`
152			`output wb_we_o;`
153			`input wb_ack_i;`
154			`output wb_cab_o;`
155			`input wb_err_i;`
156			`output [2:0] wb_cti_o;`
157			`output [1:0] wb_bte_o;`
158			`endif
159
160			`ifdef DBG_CPU0_SUPPORTED
161			`// CPU signals`
162			`input cpu0_clk_i;`
163			`output [31:0] cpu0_addr_o;`
164			`input [31:0] cpu0_data_i;`
165			`output [31:0] cpu0_data_o;`
166			`input cpu0_bp_i;`
167			`output cpu0_stall_o;`
168			`output cpu0_stb_o;`
169			`output cpu0_we_o;`
170			`input cpu0_ack_i;`
171			`output cpu0_rst_o;`
172			`endif
173
174			`ifdef DBG_CPU1_SUPPORTED
175			`input cpu1_clk_i;`
176			`output [31:0] cpu1_addr_o;`
177			`input [31:0] cpu1_data_i;`
178			`output [31:0] cpu1_data_o;`
179			`input cpu1_bp_i;`
180			`output cpu1_stall_o;`
181			`output cpu1_stb_o;`
182			`output cpu1_we_o;`
183			`input cpu1_ack_i;`
184			`output cpu1_rst_o;`
185			`endif
186
187			`ifdef DBG_JSP_SUPPORTED
188			`ifndef DBG_WISHBONE_SUPPORTED
189			`input wb_clk_i;`
190			`endif
191			`input [7:0] wb_jsp_dat_i;`
192			`input wb_jsp_stb_i;`
193			`output biu_wr_strobe;`
194			`output [7:0] jsp_data_out;`
195			`endif
196
197			`reg tdo_o;`
198			`wire tdo_wb;`
199			`wire tdo_cpu0;`
200			`wire tdo_cpu1;`
201			`wire tdo_jsp;`
202
203			`// Registers`
204			reg [`DBG_TOP_MODULE_DATA_LEN-1:0] input_shift_reg; // 1 bit sel/cmd, 4 bit opcode, 32 bit address, 16 bit length = 53 bits
205			`//reg output_shift_reg; // Just 1 bit for status (valid module selected)`
206			reg [`DBG_TOP_MODULE_ID_LENGTH -1:0] module_id_reg; // Module selection register
207
208
209			`// Control signals`
210			`wire select_cmd; // True when the command (registered at Update_DR) is for top level/module selection`
211			wire [(`DBG_TOP_MODULE_ID_LENGTH - 1) : 0] module_id_in; // The part of the input_shift_register to be used as the module select data
212			reg [(`DBG_TOP_MAX_MODULES - 1) : 0] module_selects; // Select signals for the individual modules
213			`wire select_inhibit; // OR of inhibit signals from sub-modules, prevents latching of a new module ID`
214			`wire [3:0] module_inhibit; // signals to allow submodules to prevent top level from latching new module ID`
215
216			`///////////////////////////////////////`
217			`// Combinatorial assignments`
218
219			`assign select_cmd = input_shift_reg[52];`
220			`assign module_id_in = input_shift_reg[51:50];`
221
222			`//////////////////////////////////////////////////////////`
223			`// Module select register and select signals`
224
225			`always @ (posedge tck_i or posedge rst_i)`
226			`begin`
227			`if (rst_i)`
228			`module_id_reg <= 2'b0;`
229			`else if(debug_select_i && select_cmd && update_dr_i && !select_inhibit) // Chain select`
230			`module_id_reg <= module_id_in;`
231			`end`
232
233
234			`always @ (module_id_reg)`
235			`begin`
236			module_selects = `DBG_TOP_MODULE_ID_LENGTH'h0;
237			`module_selects[module_id_reg] = 1'b1;`
238			`end`
239
240			`///////////////////////////////////////////////`
241			`// Data input shift register`
242
243			`always @ (posedge tck_i or posedge rst_i)`
244			`begin`
245			`if (rst_i)`
246			`input_shift_reg <= 53'h0;`
247			`else if(debug_select_i && shift_dr_i)`
248			`input_shift_reg <= {tdi_i, input_shift_reg[52:1]};`
249			`end`
250
251
252			`//////////////////////////////////////////////`
253			`// Debug module instantiations`
254
255			`ifdef DBG_WISHBONE_SUPPORTED
256			`// Connecting wishbone module`
257			`VARIANT`WB_MODULE i_dbg_wb (
258			`// JTAG signals`
259			`.tck_i (tck_i),`
260			`.module_tdo_o (tdo_wb),`
261			`.tdi_i (tdi_i),`
262
263			`// TAP states`
264			`.capture_dr_i (capture_dr_i),`
265			`.shift_dr_i (shift_dr_i),`
266			`.update_dr_i (update_dr_i),`
267
268			`.data_register_i (input_shift_reg),`
269			.module_select_i (module_selects[`DBG_TOP_WISHBONE_DEBUG_MODULE]),
270			.top_inhibit_o (module_inhibit[`DBG_TOP_WISHBONE_DEBUG_MODULE]),
271			`.rst_i (rst_i),`
272
273			`// WISHBONE common signals`
274			`.wb_clk_i (wb_clk_i),`
275
276			`// WISHBONE master interface`
277			`.wb_adr_o (wb_adr_o),`
278			`.wb_dat_o (wb_dat_o),`
279			`.wb_dat_i (wb_dat_i),`
280			`.wb_cyc_o (wb_cyc_o),`
281			`.wb_stb_o (wb_stb_o),`
282			`.wb_sel_o (wb_sel_o),`
283			`.wb_we_o (wb_we_o),`
284			`.wb_ack_i (wb_ack_i),`
285			`.wb_cab_o (wb_cab_o),`
286			`.wb_err_i (wb_err_i),`
287			`.wb_cti_o (wb_cti_o),`
288			`.wb_bte_o (wb_bte_o)`
289			`);`
290			`else
291			`assign tdo_wb = 1'b0;`
292			assign module_inhibit[`DBG_TOP_WISHBONE_DEBUG_MODULE] = 1'b0;
293			`endif
294
295
296
297			`ifdef DBG_CPU0_SUPPORTED
298			`VARIANT`OR1K_MODULE i_dbg_cpu_or1k (
299			`// JTAG signals`
300			`.tck_i (tck_i),`
301			`.module_tdo_o (tdo_cpu0),`
302			`.tdi_i (tdi_i),`
303
304			`// TAP states`
305			`.capture_dr_i (capture_dr_i),`
306			`.shift_dr_i (shift_dr_i),`
307			`.update_dr_i (update_dr_i),`
308
309			`.data_register_i (input_shift_reg),`
310			.module_select_i (module_selects[`DBG_TOP_CPU0_DEBUG_MODULE]),
311			.top_inhibit_o (module_inhibit[`DBG_TOP_CPU0_DEBUG_MODULE]),
312			`.rst_i (rst_i),`
313
314			`// CPU signals`
315			`.cpu_clk_i (cpu0_clk_i),`
316			`.cpu_addr_o (cpu0_addr_o),`
317			`.cpu_data_i (cpu0_data_i),`
318			`.cpu_data_o (cpu0_data_o),`
319			`.cpu_bp_i (cpu0_bp_i),`
320			`.cpu_stall_o (cpu0_stall_o),`
321			`.cpu_stb_o (cpu0_stb_o),`
322			`.cpu_we_o (cpu0_we_o),`
323			`.cpu_ack_i (cpu0_ack_i),`
324			`.cpu_rst_o (cpu0_rst_o)`
325			`);`
326			`else
327			`assign tdo_cpu0 = 1'b0;`
328			assign module_inhibit[`DBG_TOP_CPU0_DEBUG_MODULE] = 1'b0;
329			`endif // DBG_CPU0_SUPPORTED
330
331
332
333			`ifdef DBG_CPU1_SUPPORTED
334			`// Connecting cpu module`
335			`VARIANT`OR1K_MODULE i_dbg_cpu_2 (
336			`// JTAG signals`
337			`.tck_i (tck_i),`
338			`.module_tdo_o (tdo_cpu1),`
339			`.tdi_i (tdi_i),`
340
341			`// TAP states`
342			`.capture_dr_i (capture_dr_i),`
343			`.shift_dr_i (shift_dr_i),`
344			`.update_dr_i (update_dr_i),`
345
346			`.data_register_i (input_shift_reg),`
347			.module_select_i (module_selects[`DBG_TOP_CPU1_DEBUG_MODULE]),
348			.top_inhibit_o (module_inhibit[`DBG_TOP_CPU1_DEBUG_MODULE]),
349			`.rst_i (rst_i),`
350
351			`// CPU signals`
352			`.cpu_clk_i (cpu1_clk_i),`
353			`.cpu_addr_o (cpu1_addr_o),`
354			`.cpu_data_i (cpu1_data_i),`
355			`.cpu_data_o (cpu1_data_o),`
356			`.cpu_bp_i (cpu1_bp_i),`
357			`.cpu_stall_o (cpu1_stall_o),`
358			`.cpu_stb_o (cpu1_stb_o),`
359			`.cpu_we_o (cpu1_we_o),`
360			`.cpu_ack_i (cpu1_ack_i),`
361			`.cpu_rst_o (cpu1_rst_o)`
362			`);`
363			`else
364			`assign tdo_cpu1 = 1'b0;`
365			assign module_inhibit[`DBG_TOP_CPU1_DEBUG_MODULE] = 1'b0;
366			`endif
367
368			`ifdef DBG_JSP_SUPPORTED
369			`VARIANT`JFIFO_MODULE i_dbg_jfifo (
370			`// JTAG signals`
371			`.tck_i (tck_i),`
372			`.module_tdo_o (tdo_jsp),`
373			`.tdi_i (tdi_i),`
374
375			`// TAP states`
376			`.capture_dr_i (capture_dr_i),`
377			`.shift_dr_i (shift_dr_i),`
378			`.update_dr_i (update_dr_i),`
379
380			`.data_register_i (input_shift_reg),`
381			// .module_select_i (module_selects[`DBG_TOP_JSP_DEBUG_MODULE]),
382			`.module_select_i (debug_select_i),`
383			`.rst_i (rst_i),`
384
385			`// WISHBONE common signals`
386			`.wb_clk_i (wb_clk_i),`
387
388			`// WISHBONE master interface`
389			`.wb_dat_i (wb_jsp_dat_i),`
390			`.wb_stb_i (wb_jsp_stb_i),`
391			`.biu_wr_strobe (biu_wr_strobe),`
392			`.jsp_data_out (jsp_data_out)`
393
394			`);`
395
396			`else
397			`assign tdo_jsp = 1'b0;`
398
399			`endif
400
401			assign module_inhibit[`DBG_TOP_JSP_DEBUG_MODULE] = 1'b0;
402
403
404			`assign select_inhibit = \|module_inhibit;`
405
406			`/////////////////////////////////////////////////`
407			`// TDO output MUX`
408
409			`always @ (module_id_reg or tdo_wb or tdo_cpu0 or tdo_cpu1 or tdo_jsp)`
410			`begin`
411			`case (module_id_reg)`
412			`DBG_TOP_WISHBONE_DEBUG_MODULE: tdo_o = tdo_wb;
413			`DBG_TOP_CPU0_DEBUG_MODULE: tdo_o = tdo_cpu0;
414			`DBG_TOP_CPU1_DEBUG_MODULE: tdo_o = tdo_cpu1;
415			`DBG_TOP_JSP_DEBUG_MODULE: tdo_o = tdo_jsp;
416			`default: tdo_o = 1'b0;`
417			`endcase`
418			`end`
419
420
421			`endmodule`