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//////////////////////////////////////////////////////////////////////
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//// ////
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//// adbg_defines.v ////
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//// ////
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//// ////
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//// This file is part of the Advanced Debug Interface. ////
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//// ////
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//// Author(s): ////
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//// Nathan Yawn (nathan.yawn@opencores.org) ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008 - 2010 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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// Length of the MODULE ID register
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`define DBG_TOP_MODULE_ID_LENGTH 2
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// How many modules can be supported by the module id length
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`define DBG_TOP_MAX_MODULES 4
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// Chains
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`define DBG_TOP_WISHBONE_DEBUG_MODULE 2'h0
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`define DBG_TOP_CPU0_DEBUG_MODULE 2'h1
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`define DBG_TOP_CPU1_DEBUG_MODULE 2'h2
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`define DBG_TOP_JSP_DEBUG_MODULE 2'h3
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// Length of data
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`define DBG_TOP_MODULE_DATA_LEN 53
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// If WISHBONE sub-module is supported uncomment the following line
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`define DBG_WISHBONE_SUPPORTED
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// If CPU_0 sub-module is supported uncomment the following line
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`define DBG_CPU0_SUPPORTED
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// If CPU_1 sub-module is supported uncomment the following line
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//`define DBG_CPU1_SUPPORTED
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// To include the JTAG Serial Port (JSP), uncomment the following line
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`define DBG_JSP_SUPPORTED
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// Define this if you intend to use the JSP in a system with multiple
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// devices on the JTAG chain
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`define ADBG_JSP_SUPPORT_MULTI
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// If this is defined, status bits will be skipped on burst
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// reads and writes to improve download speeds.
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`define ADBG_USE_HISPEED
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