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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [xml/] [adv_dbg_if_cpu0.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
adv_debug_sys
adv_dbg_if
cpu0  default
 
 

 
 
 
 
 
 

  gen_verilog
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      cpu0
    
  

 
 
 
 
 
 
 
 
 

 
 
 
 
 

 
 
 
   
      fs-sim
 
      
        
        ../verilog/cpu0_defines.v
        verilogSource
        include
      
 
      
        
        ../verilog/adbg_or1k_defines.v
        verilogSource
        include
      
 
 
      
        
        ../verilog/adbg_top.v
        verilogSource
        module
      
 
      
        crc32
        ../verilog/adbg_crc32.v
        verilogSource
        module
      
 
 
      
        or1k_biu
        ../verilog/adbg_or1k_biu.v
        verilogSource
        module
      
 
 
      
        or1k_module
        ../verilog/adbg_or1k_module.v
        verilogSource
        module
      
 
 
      
        or1k_status_reg
        ../verilog/adbg_or1k_status_reg.v
        verilogSource
        module
      
 
 
 
 
      
        bytefifo
        ../verilog/adbg_bytefifo.v
        verilogSource
        module
      
 
      
        syncflop
        ../verilog/adbg_syncflop.v
        verilogSource
        module
      
 
      
        syncreg
        ../verilog/adbg_syncreg.v
        verilogSource
        module
      
 
 
 
   
 
 
  
 
 
 
 
 

       
 
 
              
              jtag
              
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="jtag_i"/>
              
              
 
 
              
              cpu0
              
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="cpu0_i"/>
              
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 

 
 
 

 
 
 

 
 
 
 
 
 
 
 
 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [xml/] [adv_dbg_if_cpu0.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`adv_debug_sys`
39			`adv_dbg_if`
40			`cpu0 default`
41
42
43
44
45
46	133	jt_eaton
47
48
49	134	jt_eaton
50	133	jt_eaton
51	131	jt_eaton	`gen_verilog`
52			`104.0`
53			`none`
54			`:Simulation:`
55			`./tools/verilog/gen_verilog`
56
57
58			`destination`
59			`cpu0`
60
61
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83			`fs-sim`
84
85
86
87			`../verilog/cpu0_defines.v`
88			`verilogSource`
89			`include`
90
91
92
93
94			`../verilog/adbg_or1k_defines.v`
95			`verilogSource`
96			`include`
97
98
99
100
101
102			`../verilog/adbg_top.v`
103			`verilogSource`
104			`module`
105
106
107
108			`crc32`
109			`../verilog/adbg_crc32.v`
110			`verilogSource`
111			`module`
112
113
114
115
116			`or1k_biu`
117			`../verilog/adbg_or1k_biu.v`
118			`verilogSource`
119			`module`
120
121
122
123
124			`or1k_module`
125			`../verilog/adbg_or1k_module.v`
126			`verilogSource`
127			`module`
128
129
130
131
132			`or1k_status_reg`
133			`../verilog/adbg_or1k_status_reg.v`
134			`verilogSource`
135			`module`
136
137
138
139
140
141
142			`bytefifo`
143			`../verilog/adbg_bytefifo.v`
144			`verilogSource`
145			`module`
146
147
148
149			`syncflop`
150			`../verilog/adbg_syncflop.v`
151			`verilogSource`
152			`module`
153
154
155
156			`syncreg`
157			`../verilog/adbg_syncreg.v`
158			`verilogSource`
159			`module`
160
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178			`jtag`
179
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181			`spirit:library="adv_debug_sys"`
182			`spirit:name="adv_dbg_if"`
183			`spirit:version="jtag_i"/>`
184
185
186
187
188
189			`cpu0`
190
191
192			`spirit:library="adv_debug_sys"`
193			`spirit:name="adv_dbg_if"`
194			`spirit:version="cpu0_i"/>`
195
196
197
198
199
200			`verilog`
201
202
203			`spirit:library="Testbench"`
204			`spirit:name="toolflow"`
205			`spirit:version="verilog"/>`
206
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215			`sim:Simulation:`
216			`Verilog`
217
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219			`fs-sim`
220
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225			`syn:Synthesis:`
226			`Verilog`
227
228
229			`fs-sim`
230
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234			`doc`
235
236
237			`spirit:library="Testbench"`
238			`spirit:name="toolflow"`
239			`spirit:version="documentation"/>`
240
241			`:Documentation:`
242			`Verilog`
243
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