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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [xml/] [adv_dbg_if_jfifo.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
adv_debug_sys
adv_dbg_if
jfifo  default
 
 
 
 
 
 
 
 
 
 

 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 
 
 

  gen_verilog
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      fifo
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 
 
 
 
 
 

 
 
 
 
 

 
 
 
   
      fs-sim
 
      
        
        ../verilog/jfifo_defines.v
        verilogSource
        include
      
 
 
      
        
        ../verilog/adbg_jfifo.v
        verilogSource
        module
      
 
      
        crc32
        ../verilog/adbg_crc32.v
        verilogSource
        module
      
 
      
        jfifo_biu
        ../verilog/adbg_jfifo_biu.v
        verilogSource
        module
      
 
      
        jfifo_module
        ../verilog/adbg_jfifo_module.v
        verilogSource
        module
      
 
 
      
        bytefifo
        ../verilog/adbg_bytefifo.v
        verilogSource
        module
      
 
      
        syncflop
        ../verilog/adbg_syncflop.v
        verilogSource
        module
      
 
      
        syncreg
        ../verilog/adbg_syncreg.v
        verilogSource
        module
      
 
 
   
 
 
 
 
 
 
 
   
      fs-syn
 
      
        
        ../verilog/SYNTHESYS
        verilogSource
        include
      
 
 
      
        
        ../verilog/jfifo_defines.v
        verilogSource
        include
      
 
 
      
        
        ../verilog/adbg_jfifo.v
        verilogSource
        module
      
 
      
        crc32
        ../verilog/adbg_crc32.v
        verilogSource
        module
      
 
      
        jfifo_biu
        ../verilog/adbg_jfifo_biu.v
        verilogSource
        module
      
 
      
        jfifo_module
        ../verilog/adbg_jfifo_module.v
        verilogSource
        module
      
 
 
      
        bytefifo
        ../verilog/adbg_bytefifo.v
        verilogSource
        module
      
 
      
        syncflop
        ../verilog/adbg_syncflop.v
        verilogSource
        module
      
 
      
        syncreg
        ../verilog/adbg_syncreg.v
        verilogSource
        module
      
 
 
   
 
 
 
 
 
 
 
 
 
 
 
  
 
 
 
 
 

       
 
 
              
              jtag
              
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="jtag_i"/>
              
              
 
 
 
              
              jfifo
              
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="jfifo_i"/>
              
              
 
 
 
 
 
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 

 
 

jsp_data_out
wire
out70

 
 

biu_wr_strobe
wire
out

 
 
 
 

 
 
 

 
 
 
 
 
 
 
 
 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [xml/] [adv_dbg_if_jfifo.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`adv_debug_sys`
39			`adv_dbg_if`
40			`jfifo default`
41
42
43
44
45
46
47
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49
50
51
52
53
54
55	133	jt_eaton	`elab_verilog`
56			`102.1`
57			`none`
58			`:Simulation:`
59			`./tools/verilog/elab_verilog`
60
61
62			`dest_dir`
63			`io_ports`
64
65
66
67
68
69
70
71
72
73	131	jt_eaton	`gen_verilog`
74			`104.0`
75			`none`
76			`:Simulation:`
77			`./tools/verilog/gen_verilog`
78
79
80			`destination`
81			`fifo`
82
83
84			`dest_dir`
85			`../verilog`
86
87
88
89
90
91
92
93
94
95
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97
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99
100
101
102
103
104
105
106
107
108
109			`fs-sim`
110
111
112
113			`../verilog/jfifo_defines.v`
114			`verilogSource`
115			`include`
116
117
118
119
120
121			`../verilog/adbg_jfifo.v`
122			`verilogSource`
123			`module`
124
125
126
127			`crc32`
128			`../verilog/adbg_crc32.v`
129			`verilogSource`
130			`module`
131
132
133
134			`jfifo_biu`
135			`../verilog/adbg_jfifo_biu.v`
136			`verilogSource`
137			`module`
138
139
140
141			`jfifo_module`
142			`../verilog/adbg_jfifo_module.v`
143			`verilogSource`
144			`module`
145
146
147
148
149			`bytefifo`
150			`../verilog/adbg_bytefifo.v`
151			`verilogSource`
152			`module`
153
154
155
156			`syncflop`
157			`../verilog/adbg_syncflop.v`
158			`verilogSource`
159			`module`
160
161
162
163			`syncreg`
164			`../verilog/adbg_syncreg.v`
165			`verilogSource`
166			`module`
167
168
169
170
171
172
173
174
175
176
177
178
179			`fs-syn`
180
181
182
183			`../verilog/SYNTHESYS`
184			`verilogSource`
185			`include`
186
187
188
189
190
191			`../verilog/jfifo_defines.v`
192			`verilogSource`
193			`include`
194
195
196
197
198
199			`../verilog/adbg_jfifo.v`
200			`verilogSource`
201			`module`
202
203
204
205			`crc32`
206			`../verilog/adbg_crc32.v`
207			`verilogSource`
208			`module`
209
210
211
212			`jfifo_biu`
213			`../verilog/adbg_jfifo_biu.v`
214			`verilogSource`
215			`module`
216
217
218
219			`jfifo_module`
220			`../verilog/adbg_jfifo_module.v`
221			`verilogSource`
222			`module`
223
224
225
226
227			`bytefifo`
228			`../verilog/adbg_bytefifo.v`
229			`verilogSource`
230			`module`
231
232
233
234			`syncflop`
235			`../verilog/adbg_syncflop.v`
236			`verilogSource`
237			`module`
238
239
240
241			`syncreg`
242			`../verilog/adbg_syncreg.v`
243			`verilogSource`
244			`module`
245
246
247
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249
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251
252
253
254
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265
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268
269
270
271			`jtag`
272
273
274			`spirit:library="adv_debug_sys"`
275			`spirit:name="adv_dbg_if"`
276			`spirit:version="jtag_i"/>`
277
278
279
280
281
282
283			`jfifo`
284
285
286			`spirit:library="adv_debug_sys"`
287			`spirit:name="adv_dbg_if"`
288			`spirit:version="jfifo_i"/>`
289
290
291
292
293
294
295
296
297
298
299			`verilog`
300
301
302			`spirit:library="Testbench"`
303			`spirit:name="toolflow"`
304			`spirit:version="verilog"/>`
305
306
307
308
309
310
311
312
313
314			`sim:Simulation:`
315			`Verilog`
316
317
318			`fs-sim`
319
320
321
322
323
324			`syn:Synthesis:`
325			`Verilog`
326
327
328			`fs-syn`
329
330
331
332
333
334
335			`doc`
336
337
338			`spirit:library="Testbench"`
339			`spirit:name="toolflow"`
340			`spirit:version="documentation"/>`
341
342			`:Documentation:`
343			`Verilog`
344
345
346
347
348
349
350
351
352
353
354
355
356
357			`jsp_data_out`
358			`wire`
359			`out70`
360
361
362
363
364			`biu_wr_strobe`
365			`wire`
366			`out`
367
368
369
370
371
372
373
374
375
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