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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [xml/] [adv_dbg_if_jsp.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
adv_debug_sys
adv_dbg_if
jsp  default
 
 
 
 
 
 
 
 
 
 

 
 

  gen_verilog
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
 
    
      destination
      jsp
    
 
    
      dest_dir
      ../verilog
    
  

 
 
 
 
 
 
 
 
 

 
 
 
 
 

 
 
 
   
      fs-sim
 
      
        
        ../verilog/jsp_defines.v
        verilogSource
        include
      
 
 
      
        
        ../verilog/adbg_top.v
        verilogSource
        module
      
 
      
        crc32
        ../verilog/adbg_crc32.v
        verilogSource
        module
      
 
      
        jsp_biu
        ../verilog/adbg_jsp_biu.v
        verilogSource
        module
      
 
      
        jsp_module
        ../verilog/adbg_jsp_module.v
        verilogSource
        module
      
 
 
      
        bytefifo
        ../verilog/adbg_bytefifo.v
        verilogSource
        module
      
 
      
        syncflop
        ../verilog/adbg_syncflop.v
        verilogSource
        module
      
 
      
        syncreg
        ../verilog/adbg_syncreg.v
        verilogSource
        module
      
 
 
 
   
 
 
  
 
 
 
 
 

       
 
 
              
              jtag
              
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="jtag_i"/>
              
              
 
 
 
              
              jsp
              
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="jsp_i"/>
              
              
 
 
 
 
 
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 

 
 
int_o
wire
out

 
 
biu_wr_strobe
wire
out

 
 
 
 

jsp_data_out
reg
out70

 
 
 

 
 
 

 
 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [xml/] [adv_dbg_if_jsp.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`adv_debug_sys`
39			`adv_dbg_if`
40			`jsp default`
41
42
43
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45
46
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49
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51
52
53
54
55			`gen_verilog`
56			`104.0`
57			`none`
58			`:Simulation:`
59			`./tools/verilog/gen_verilog`
60
61
62
63			`destination`
64			`jsp`
65
66
67
68			`dest_dir`
69			`../verilog`
70
71
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73
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93			`fs-sim`
94
95
96
97			`../verilog/jsp_defines.v`
98			`verilogSource`
99			`include`
100
101
102
103
104
105			`../verilog/adbg_top.v`
106			`verilogSource`
107			`module`
108
109
110
111			`crc32`
112			`../verilog/adbg_crc32.v`
113			`verilogSource`
114			`module`
115
116
117
118			`jsp_biu`
119			`../verilog/adbg_jsp_biu.v`
120			`verilogSource`
121			`module`
122
123
124
125			`jsp_module`
126			`../verilog/adbg_jsp_module.v`
127			`verilogSource`
128			`module`
129
130
131
132
133			`bytefifo`
134			`../verilog/adbg_bytefifo.v`
135			`verilogSource`
136			`module`
137
138
139
140			`syncflop`
141			`../verilog/adbg_syncflop.v`
142			`verilogSource`
143			`module`
144
145
146
147			`syncreg`
148			`../verilog/adbg_syncreg.v`
149			`verilogSource`
150			`module`
151
152
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167
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169			`jtag`
170
171
172			`spirit:library="adv_debug_sys"`
173			`spirit:name="adv_dbg_if"`
174			`spirit:version="jtag_i"/>`
175
176
177
178
179
180
181			`jsp`
182
183
184			`spirit:library="adv_debug_sys"`
185			`spirit:name="adv_dbg_if"`
186			`spirit:version="jsp_i"/>`
187
188
189
190
191
192
193
194
195
196
197			`verilog`
198
199
200			`spirit:library="Testbench"`
201			`spirit:name="toolflow"`
202			`spirit:version="verilog"/>`
203
204
205
206
207
208
209
210
211
212			`sim:Simulation:`
213			`Verilog`
214
215
216			`fs-sim`
217
218
219
220
221
222			`syn:Synthesis:`
223			`Verilog`
224
225
226			`fs-sim`
227
228
229
230
231			`doc`
232
233
234			`spirit:library="Testbench"`
235			`spirit:name="toolflow"`
236			`spirit:version="documentation"/>`
237
238			`:Documentation:`
239			`Verilog`
240
241
242
243
244
245
246
247
248
249
250
251
252			`int_o`
253			`wire`
254			`out`
255
256
257
258			`biu_wr_strobe`
259			`wire`
260			`out`
261
262
263
264
265
266
267			`jsp_data_out`
268			`reg`
269			`out70`
270
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