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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [xml/] [adv_dbg_if_jsp.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
adv_debug_sys
adv_dbg_if
jsp  default
 
 
 
 
 
 
 
 
 
 

 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 
 

  gen_verilog
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      jsp
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 
 
 
 
 
 

 
 
 
 
 

 
 
 
   
      fs-sim
 
      
        
        ../verilog/jsp_defines.v
        verilogSource
        include
      
 
 
      
        
        ../verilog/adbg_top.v
        verilogSource
        module
      
 
      
        crc32
        ../verilog/adbg_crc32.v
        verilogSource
        module
      
 
      
        jsp_biu
        ../verilog/adbg_jsp_biu.v
        verilogSource
        module
      
 
      
        jsp_module
        ../verilog/adbg_jsp_module.v
        verilogSource
        module
      
 
 
      
        bytefifo
        ../verilog/adbg_bytefifo.v
        verilogSource
        module
      
 
      
        syncflop
        ../verilog/adbg_syncflop.v
        verilogSource
        module
      
 
      
        syncreg
        ../verilog/adbg_syncreg.v
        verilogSource
        module
      
 
 
 
   
 
 
  
 
 
 
 
 

       
 
 
              
              jtag
              
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="jtag_i"/>
              
              
 
 
 
              
              jsp
              
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="jsp_i"/>
              
              
 
 
 
 
 
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 

 
 
int_o
wire
out

 
 
biu_wr_strobe
wire
out

 
 
 
 

jsp_data_out
reg
out70

 
 
 

 
 
 

 
 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [xml/] [adv_dbg_if_jsp.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`adv_debug_sys`
39			`adv_dbg_if`
40			`jsp default`
41
42
43
44
45
46
47
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49
50
51
52
53
54
55	133	jt_eaton	`elab_verilog`
56			`102.1`
57			`none`
58			`:Simulation:`
59			`./tools/verilog/elab_verilog`
60
61
62			`dest_dir`
63			`io_ports`
64
65
66
67
68
69
70
71
72	131	jt_eaton	`gen_verilog`
73			`104.0`
74			`none`
75			`:Simulation:`
76			`./tools/verilog/gen_verilog`
77
78
79			`destination`
80			`jsp`
81
82
83			`dest_dir`
84			`../verilog`
85
86
87
88
89
90
91
92
93
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95
96
97
98
99
100
101
102
103
104
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106
107
108			`fs-sim`
109
110
111
112			`../verilog/jsp_defines.v`
113			`verilogSource`
114			`include`
115
116
117
118
119
120			`../verilog/adbg_top.v`
121			`verilogSource`
122			`module`
123
124
125
126			`crc32`
127			`../verilog/adbg_crc32.v`
128			`verilogSource`
129			`module`
130
131
132
133			`jsp_biu`
134			`../verilog/adbg_jsp_biu.v`
135			`verilogSource`
136			`module`
137
138
139
140			`jsp_module`
141			`../verilog/adbg_jsp_module.v`
142			`verilogSource`
143			`module`
144
145
146
147
148			`bytefifo`
149			`../verilog/adbg_bytefifo.v`
150			`verilogSource`
151			`module`
152
153
154
155			`syncflop`
156			`../verilog/adbg_syncflop.v`
157			`verilogSource`
158			`module`
159
160
161
162			`syncreg`
163			`../verilog/adbg_syncreg.v`
164			`verilogSource`
165			`module`
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184			`jtag`
185
186
187			`spirit:library="adv_debug_sys"`
188			`spirit:name="adv_dbg_if"`
189			`spirit:version="jtag_i"/>`
190
191
192
193
194
195
196			`jsp`
197
198
199			`spirit:library="adv_debug_sys"`
200			`spirit:name="adv_dbg_if"`
201			`spirit:version="jsp_i"/>`
202
203
204
205
206
207
208
209
210
211
212			`verilog`
213
214
215			`spirit:library="Testbench"`
216			`spirit:name="toolflow"`
217			`spirit:version="verilog"/>`
218
219
220
221
222
223
224
225
226
227			`sim:Simulation:`
228			`Verilog`
229
230
231			`fs-sim`
232
233
234
235
236
237			`syn:Synthesis:`
238			`Verilog`
239
240
241			`fs-sim`
242
243
244
245
246			`doc`
247
248
249			`spirit:library="Testbench"`
250			`spirit:name="toolflow"`
251			`spirit:version="documentation"/>`
252
253			`:Documentation:`
254			`Verilog`
255
256
257
258
259
260
261
262
263
264
265
266
267			`int_o`
268			`wire`
269			`out`
270
271
272
273			`biu_wr_strobe`
274			`wire`
275			`out`
276
277
278
279
280
281
282			`jsp_data_out`
283			`reg`
284			`out70`
285
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