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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [xml/] [adv_dbg_if_jsp.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
adv_debug_sys
adv_dbg_if
jsp  default
 
 
 
 
 
 
 
 
 
 

 
 
 
 
 
 
 

  gen_verilog
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      jsp
    
  

 
 
 
 
 
 
 
 
 

 
 
 
 
 

 
 
 
   
      fs-sim
 
      
        
        ../verilog/jsp_defines.v
        verilogSource
        include
      
 
 
      
        
        ../verilog/adbg_top.v
        verilogSource
        module
      
 
      
        crc32
        ../verilog/adbg_crc32.v
        verilogSource
        module
      
 
      
        jsp_biu
        ../verilog/adbg_jsp_biu.v
        verilogSource
        module
      
 
      
        jsp_module
        ../verilog/adbg_jsp_module.v
        verilogSource
        module
      
 
 
      
        bytefifo
        ../verilog/adbg_bytefifo.v
        verilogSource
        module
      
 
      
        syncflop
        ../verilog/adbg_syncflop.v
        verilogSource
        module
      
 
      
        syncreg
        ../verilog/adbg_syncreg.v
        verilogSource
        module
      
 
 
 
   
 
 
  
 
 
 
 
 

       
 
 
              
              jtag
              
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="jtag_i"/>
              
              
 
 
 
              
              jsp
              
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="jsp_i"/>
              
              
 
 
 
 
 
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 

 
 
int_o
wire
out

 
 
biu_wr_strobe
wire
out

 
 
 
 

jsp_data_out
reg
out70

 
 
 

 
 
 

 
 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [xml/] [adv_dbg_if_jsp.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	134	jt_eaton
2	131	jt_eaton
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`adv_debug_sys`
39			`adv_dbg_if`
40			`jsp default`
41
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54	133	jt_eaton
55
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58	134	jt_eaton
59	133	jt_eaton
60	131	jt_eaton	`gen_verilog`
61			`104.0`
62			`none`
63			`:Simulation:`
64			`./tools/verilog/gen_verilog`
65
66
67			`destination`
68			`jsp`
69
70
71
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82
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91
92			`fs-sim`
93
94
95
96			`../verilog/jsp_defines.v`
97			`verilogSource`
98			`include`
99
100
101
102
103
104			`../verilog/adbg_top.v`
105			`verilogSource`
106			`module`
107
108
109
110			`crc32`
111			`../verilog/adbg_crc32.v`
112			`verilogSource`
113			`module`
114
115
116
117			`jsp_biu`
118			`../verilog/adbg_jsp_biu.v`
119			`verilogSource`
120			`module`
121
122
123
124			`jsp_module`
125			`../verilog/adbg_jsp_module.v`
126			`verilogSource`
127			`module`
128
129
130
131
132			`bytefifo`
133			`../verilog/adbg_bytefifo.v`
134			`verilogSource`
135			`module`
136
137
138
139			`syncflop`
140			`../verilog/adbg_syncflop.v`
141			`verilogSource`
142			`module`
143
144
145
146			`syncreg`
147			`../verilog/adbg_syncreg.v`
148			`verilogSource`
149			`module`
150
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166
167
168			`jtag`
169
170
171			`spirit:library="adv_debug_sys"`
172			`spirit:name="adv_dbg_if"`
173			`spirit:version="jtag_i"/>`
174
175
176
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178
179
180			`jsp`
181
182
183			`spirit:library="adv_debug_sys"`
184			`spirit:name="adv_dbg_if"`
185			`spirit:version="jsp_i"/>`
186
187
188
189
190
191
192
193
194
195
196			`verilog`
197
198
199			`spirit:library="Testbench"`
200			`spirit:name="toolflow"`
201			`spirit:version="verilog"/>`
202
203
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205
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208
209
210
211			`sim:Simulation:`
212			`Verilog`
213
214
215			`fs-sim`
216
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220
221			`syn:Synthesis:`
222			`Verilog`
223
224
225			`fs-sim`
226
227
228
229
230			`doc`
231
232
233			`spirit:library="Testbench"`
234			`spirit:name="toolflow"`
235			`spirit:version="documentation"/>`
236
237			`:Documentation:`
238			`Verilog`
239
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249
250
251			`int_o`
252			`wire`
253			`out`
254
255
256
257			`biu_wr_strobe`
258			`wire`
259			`out`
260
261
262
263
264
265
266			`jsp_data_out`
267			`reg`
268			`out70`
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