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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [xml/] [adv_dbg_if_wb.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
adv_debug_sys
adv_dbg_if
wb  default
 
 
 
 
 
 

 
 

  gen_verilog
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
 
 
    
      destination
      wb
    
 
    
      dest_dir
      ../verilog
    
  

 
 
 
 
 
 
 
 
 

 
 
 
 
 

 
 
 
   
      fs-sim
 
      
        
        ../verilog/wb_defines.v
        verilogSource
        include
      
 
      
        
        ../verilog/adbg_wb_defines.v
        verilogSource
        include
      
 
      
        
        ../verilog/adbg_top.v
        verilogSource
        module
      
 
      
        crc32
        ../verilog/adbg_crc32.v
        verilogSource
        module
      
 
      
        wb_biu
        ../verilog/adbg_wb_biu.v
        verilogSource
        module
      
 
      
        wb_module
        ../verilog/adbg_wb_module.v
        verilogSource
        module
      
 
 
      
        bytefifo
        ../verilog/adbg_bytefifo.v
        verilogSource
        module
      
 
      
        syncflop
        ../verilog/adbg_syncflop.v
        verilogSource
        module
      
 
      
        syncreg
        ../verilog/adbg_syncreg.v
        verilogSource
        module
      
 
 
 
   
 
 
  
 
 
 
 
 

       
 
 
              
              jtag
              
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="jtag_i"/>
              
              
 
 
              
              wb
              
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="wb_i"/>
              
              
 
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 
 
 
 

 
 
 
 
 
 
 
 
 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [xml/] [adv_dbg_if_wb.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`adv_debug_sys`
39			`adv_dbg_if`
40			`wb default`
41
42
43
44
45
46
47
48
49
50
51			`gen_verilog`
52			`104.0`
53			`none`
54			`:Simulation:`
55			`./tools/verilog/gen_verilog`
56
57
58
59
60			`destination`
61			`wb`
62
63
64
65			`dest_dir`
66			`../verilog`
67
68
69
70
71
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73
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89
90			`fs-sim`
91
92
93
94			`../verilog/wb_defines.v`
95			`verilogSource`
96			`include`
97
98
99
100
101			`../verilog/adbg_wb_defines.v`
102			`verilogSource`
103			`include`
104
105
106
107
108			`../verilog/adbg_top.v`
109			`verilogSource`
110			`module`
111
112
113
114			`crc32`
115			`../verilog/adbg_crc32.v`
116			`verilogSource`
117			`module`
118
119
120
121			`wb_biu`
122			`../verilog/adbg_wb_biu.v`
123			`verilogSource`
124			`module`
125
126
127
128			`wb_module`
129			`../verilog/adbg_wb_module.v`
130			`verilogSource`
131			`module`
132
133
134
135
136			`bytefifo`
137			`../verilog/adbg_bytefifo.v`
138			`verilogSource`
139			`module`
140
141
142
143			`syncflop`
144			`../verilog/adbg_syncflop.v`
145			`verilogSource`
146			`module`
147
148
149
150			`syncreg`
151			`../verilog/adbg_syncreg.v`
152			`verilogSource`
153			`module`
154
155
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167
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170
171
172			`jtag`
173
174
175			`spirit:library="adv_debug_sys"`
176			`spirit:name="adv_dbg_if"`
177			`spirit:version="jtag_i"/>`
178
179
180
181
182
183			`wb`
184
185
186			`spirit:library="adv_debug_sys"`
187			`spirit:name="adv_dbg_if"`
188			`spirit:version="wb_i"/>`
189
190
191
192
193
194
195			`verilog`
196
197
198			`spirit:library="Testbench"`
199			`spirit:name="toolflow"`
200			`spirit:version="verilog"/>`
201
202
203
204
205
206
207
208
209
210			`sim:Simulation:`
211			`Verilog`
212
213
214			`fs-sim`
215
216
217
218
219
220			`syn:Synthesis:`
221			`Verilog`
222
223
224			`fs-sim`
225
226
227
228
229			`doc`
230
231
232			`spirit:library="Testbench"`
233			`spirit:name="toolflow"`
234			`spirit:version="documentation"/>`
235
236			`:Documentation:`
237			`Verilog`
238
239
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