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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [xml/] [adv_dbg_if_wb.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
adv_debug_sys
adv_dbg_if
wb  default
 
 
 
 
 
 

 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      configuration
      default
    
    
      dest_dir
      io_ports
    
  

 
 
 
 

  gen_verilog
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      wb
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 
 
 
 
 
 

 
 
 
 
 

 
 
 
   
      fs-sim
 
      
        
        ../verilog/wb_defines.v
        verilogSource
        include
      
 
      
        
        ../verilog/adbg_wb_defines.v
        verilogSource
        include
      
 
      
        
        ../verilog/adbg_top.v
        verilogSource
        module
      
 
      
        crc32
        ../verilog/adbg_crc32.v
        verilogSource
        module
      
 
      
        wb_biu
        ../verilog/adbg_wb_biu.v
        verilogSource
        module
      
 
      
        wb_module
        ../verilog/adbg_wb_module.v
        verilogSource
        module
      
 
 
      
        bytefifo
        ../verilog/adbg_bytefifo.v
        verilogSource
        module
      
 
      
        syncflop
        ../verilog/adbg_syncflop.v
        verilogSource
        module
      
 
      
        syncreg
        ../verilog/adbg_syncreg.v
        verilogSource
        module
      
 
 
 
   
 
 
  
 
 
 
 
 

       
 
 
              
              jtag
              
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="jtag_i"/>
              
              
 
 
              
              wb
              
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="wb_i"/>
              
              
 
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 
 
 
 

 
 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [xml/] [adv_dbg_if_wb.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`adv_debug_sys`
39			`adv_dbg_if`
40			`wb default`
41
42
43
44
45
46
47
48
49
50
51	133	jt_eaton	`elab_verilog`
52			`102.1`
53			`none`
54			`:Simulation:`
55			`./tools/verilog/elab_verilog`
56
57
58			`configuration`
59			`default`
60
61
62			`dest_dir`
63			`io_ports`
64
65
66
67
68
69
70
71
72	131	jt_eaton	`gen_verilog`
73			`104.0`
74			`none`
75			`:Simulation:`
76			`./tools/verilog/gen_verilog`
77
78
79			`destination`
80			`wb`
81
82
83			`dest_dir`
84			`../verilog`
85
86
87
88
89
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107
108			`fs-sim`
109
110
111
112			`../verilog/wb_defines.v`
113			`verilogSource`
114			`include`
115
116
117
118
119			`../verilog/adbg_wb_defines.v`
120			`verilogSource`
121			`include`
122
123
124
125
126			`../verilog/adbg_top.v`
127			`verilogSource`
128			`module`
129
130
131
132			`crc32`
133			`../verilog/adbg_crc32.v`
134			`verilogSource`
135			`module`
136
137
138
139			`wb_biu`
140			`../verilog/adbg_wb_biu.v`
141			`verilogSource`
142			`module`
143
144
145
146			`wb_module`
147			`../verilog/adbg_wb_module.v`
148			`verilogSource`
149			`module`
150
151
152
153
154			`bytefifo`
155			`../verilog/adbg_bytefifo.v`
156			`verilogSource`
157			`module`
158
159
160
161			`syncflop`
162			`../verilog/adbg_syncflop.v`
163			`verilogSource`
164			`module`
165
166
167
168			`syncreg`
169			`../verilog/adbg_syncreg.v`
170			`verilogSource`
171			`module`
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190			`jtag`
191
192
193			`spirit:library="adv_debug_sys"`
194			`spirit:name="adv_dbg_if"`
195			`spirit:version="jtag_i"/>`
196
197
198
199
200
201			`wb`
202
203
204			`spirit:library="adv_debug_sys"`
205			`spirit:name="adv_dbg_if"`
206			`spirit:version="wb_i"/>`
207
208
209
210
211
212
213			`verilog`
214
215
216			`spirit:library="Testbench"`
217			`spirit:name="toolflow"`
218			`spirit:version="verilog"/>`
219
220
221
222
223
224
225
226
227
228			`sim:Simulation:`
229			`Verilog`
230
231
232			`fs-sim`
233
234
235
236
237
238			`syn:Synthesis:`
239			`Verilog`
240
241
242			`fs-sim`
243
244
245
246
247			`doc`
248
249
250			`spirit:library="Testbench"`
251			`spirit:name="toolflow"`
252			`spirit:version="documentation"/>`
253
254			`:Documentation:`
255			`Verilog`
256
257
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