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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [xml/] [adv_dbg_if_wb_cpu0_jfifo.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
adv_debug_sys
adv_dbg_if
wb_cpu0_jfifo  default
 
 
 
 
 
 
 
 
 
 

 
 

  gen_verilog
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
 
 
    
      destination
      wb_cpu0_jfifo
    
 
    
      dest_dir
      ../verilog
    
  

 
 
 
 
 
 
 
 
 

 
 
 
 
 

 
 
 
   
      fs-sim
 
      
        
        ../verilog/wb_cpu0_jfifo_defines.v
        verilogSource
        include
      
 
      
        
        ../verilog/adbg_or1k_defines.v
        verilogSource
        include
      
 
      
        
        ../verilog/adbg_wb_defines.v
        verilogSource
        include
      
 
      
        
        ../verilog/adbg_wb_cpu0_jfifo.v
        verilogSource
        module
      
 
      
        crc32
        ../verilog/adbg_crc32.v
        verilogSource
        module
      
 
      
        jfifo_biu
        ../verilog/adbg_jfifo_biu.v
        verilogSource
        module
      
 
      
        jfifo_module
        ../verilog/adbg_jfifo_module.v
        verilogSource
        module
      
 
      
        or1k_biu
        ../verilog/adbg_or1k_biu.v
        verilogSource
        module
      
 
 
      
        or1k_module
        ../verilog/adbg_or1k_module.v
        verilogSource
        module
      
 
 
      
        or1k_status_reg
        ../verilog/adbg_or1k_status_reg.v
        verilogSource
        module
      
 
 
      
        wb_biu
        ../verilog/adbg_wb_biu.v
        verilogSource
        module
      
 
      
        wb_module
        ../verilog/adbg_wb_module.v
        verilogSource
        module
      
 
 
      
        bytefifo
        ../verilog/adbg_bytefifo.v
        verilogSource
        module
      
 
      
        syncflop
        ../verilog/adbg_syncflop.v
        verilogSource
        module
      
 
      
        syncreg
        ../verilog/adbg_syncreg.v
        verilogSource
        module
      
 
 
 
   
 
 
 
 
   
      fs-syn
 
 
      
        
        ../verilog/SYNTHESYS
        verilogSource
        include
      
 
 
      
        
        ../verilog/wb_cpu0_jfifo_defines.v
        verilogSource
        include
      
 
      
        
        ../verilog/adbg_or1k_defines.v
        verilogSource
        include
      
 
      
        
        ../verilog/adbg_wb_defines.v
        verilogSource
        include
      
 
      
        
        ../verilog/adbg_wb_cpu0_jfifo.v
        verilogSource
        module
      
 
      
        crc32
        ../verilog/adbg_crc32.v
        verilogSource
        module
      
 
      
        jfifo_biu
        ../verilog/adbg_jfifo_biu.v
        verilogSource
        module
      
 
      
        jfifo_module
        ../verilog/adbg_jfifo_module.v
        verilogSource
        module
      
 
      
        or1k_biu
        ../verilog/adbg_or1k_biu.v
        verilogSource
        module
      
 
 
      
        or1k_module
        ../verilog/adbg_or1k_module.v
        verilogSource
        module
      
 
 
      
        or1k_status_reg
        ../verilog/adbg_or1k_status_reg.v
        verilogSource
        module
      
 
 
      
        wb_biu
        ../verilog/adbg_wb_biu.v
        verilogSource
        module
      
 
      
        wb_module
        ../verilog/adbg_wb_module.v
        verilogSource
        module
      
 
 
      
        bytefifo
        ../verilog/adbg_bytefifo.v
        verilogSource
        module
      
 
      
        syncflop
        ../verilog/adbg_syncflop.v
        verilogSource
        module
      
 
      
        syncreg
        ../verilog/adbg_syncreg.v
        verilogSource
        module
      
 
 
 
   
 
 
  
 
 
 
 
 

       
 
 
              
              jtag
              
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="jtag_i"/>
              
              
 
 
              
              cpu0
              
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="cpu0_i"/>
              
              
 
 
              
              wb
              
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="wb_i"/>
              
              
 
 
 
 
              
              jfifo
              
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="jfifo_i"/>
              
              
 
 
 
 
 
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 

 
 
int_o
wire
out

 
 
 
 
biu_wr_strobe
wire
out

 
 
 
 

jsp_data_out
reg
out70

 
 
 

 
 
 

 
 
 
 
 
 
 
 
 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [rtl/] [xml/] [adv_dbg_if_wb_cpu0_jfifo.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`adv_debug_sys`
39			`adv_dbg_if`
40			`wb_cpu0_jfifo default`
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55			`gen_verilog`
56			`104.0`
57			`none`
58			`:Simulation:`
59			`./tools/verilog/gen_verilog`
60
61
62
63
64			`destination`
65			`wb_cpu0_jfifo`
66
67
68
69			`dest_dir`
70			`../verilog`
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94			`fs-sim`
95
96
97
98			`../verilog/wb_cpu0_jfifo_defines.v`
99			`verilogSource`
100			`include`
101
102
103
104
105			`../verilog/adbg_or1k_defines.v`
106			`verilogSource`
107			`include`
108
109
110
111
112			`../verilog/adbg_wb_defines.v`
113			`verilogSource`
114			`include`
115
116
117
118
119			`../verilog/adbg_wb_cpu0_jfifo.v`
120			`verilogSource`
121			`module`
122
123
124
125			`crc32`
126			`../verilog/adbg_crc32.v`
127			`verilogSource`
128			`module`
129
130
131
132			`jfifo_biu`
133			`../verilog/adbg_jfifo_biu.v`
134			`verilogSource`
135			`module`
136
137
138
139			`jfifo_module`
140			`../verilog/adbg_jfifo_module.v`
141			`verilogSource`
142			`module`
143
144
145
146			`or1k_biu`
147			`../verilog/adbg_or1k_biu.v`
148			`verilogSource`
149			`module`
150
151
152
153
154			`or1k_module`
155			`../verilog/adbg_or1k_module.v`
156			`verilogSource`
157			`module`
158
159
160
161
162			`or1k_status_reg`
163			`../verilog/adbg_or1k_status_reg.v`
164			`verilogSource`
165			`module`
166
167
168
169
170			`wb_biu`
171			`../verilog/adbg_wb_biu.v`
172			`verilogSource`
173			`module`
174
175
176
177			`wb_module`
178			`../verilog/adbg_wb_module.v`
179			`verilogSource`
180			`module`
181
182
183
184
185			`bytefifo`
186			`../verilog/adbg_bytefifo.v`
187			`verilogSource`
188			`module`
189
190
191
192			`syncflop`
193			`../verilog/adbg_syncflop.v`
194			`verilogSource`
195			`module`
196
197
198
199			`syncreg`
200			`../verilog/adbg_syncreg.v`
201			`verilogSource`
202			`module`
203
204
205
206
207
208
209
210
211
212
213			`fs-syn`
214
215
216
217
218			`../verilog/SYNTHESYS`
219			`verilogSource`
220			`include`
221
222
223
224
225
226			`../verilog/wb_cpu0_jfifo_defines.v`
227			`verilogSource`
228			`include`
229
230
231
232
233			`../verilog/adbg_or1k_defines.v`
234			`verilogSource`
235			`include`
236
237
238
239
240			`../verilog/adbg_wb_defines.v`
241			`verilogSource`
242			`include`
243
244
245
246
247			`../verilog/adbg_wb_cpu0_jfifo.v`
248			`verilogSource`
249			`module`
250
251
252
253			`crc32`
254			`../verilog/adbg_crc32.v`
255			`verilogSource`
256			`module`
257
258
259
260			`jfifo_biu`
261			`../verilog/adbg_jfifo_biu.v`
262			`verilogSource`
263			`module`
264
265
266
267			`jfifo_module`
268			`../verilog/adbg_jfifo_module.v`
269			`verilogSource`
270			`module`
271
272
273
274			`or1k_biu`
275			`../verilog/adbg_or1k_biu.v`
276			`verilogSource`
277			`module`
278
279
280
281
282			`or1k_module`
283			`../verilog/adbg_or1k_module.v`
284			`verilogSource`
285			`module`
286
287
288
289
290			`or1k_status_reg`
291			`../verilog/adbg_or1k_status_reg.v`
292			`verilogSource`
293			`module`
294
295
296
297
298			`wb_biu`
299			`../verilog/adbg_wb_biu.v`
300			`verilogSource`
301			`module`
302
303
304
305			`wb_module`
306			`../verilog/adbg_wb_module.v`
307			`verilogSource`
308			`module`
309
310
311
312
313			`bytefifo`
314			`../verilog/adbg_bytefifo.v`
315			`verilogSource`
316			`module`
317
318
319
320			`syncflop`
321			`../verilog/adbg_syncflop.v`
322			`verilogSource`
323			`module`
324
325
326
327			`syncreg`
328			`../verilog/adbg_syncreg.v`
329			`verilogSource`
330			`module`
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349			`jtag`
350
351
352			`spirit:library="adv_debug_sys"`
353			`spirit:name="adv_dbg_if"`
354			`spirit:version="jtag_i"/>`
355
356
357
358
359
360			`cpu0`
361
362
363			`spirit:library="adv_debug_sys"`
364			`spirit:name="adv_dbg_if"`
365			`spirit:version="cpu0_i"/>`
366
367
368
369
370
371			`wb`
372
373
374			`spirit:library="adv_debug_sys"`
375			`spirit:name="adv_dbg_if"`
376			`spirit:version="wb_i"/>`
377
378
379
380
381
382
383
384			`jfifo`
385
386
387			`spirit:library="adv_debug_sys"`
388			`spirit:name="adv_dbg_if"`
389			`spirit:version="jfifo_i"/>`
390
391
392
393
394
395
396
397
398
399
400			`verilog`
401
402
403			`spirit:library="Testbench"`
404			`spirit:name="toolflow"`
405			`spirit:version="verilog"/>`
406
407
408
409
410
411
412
413
414
415			`sim:Simulation:`
416			`Verilog`
417
418
419			`fs-sim`
420
421
422
423
424
425			`syn:Synthesis:`
426			`Verilog`
427
428
429			`fs-syn`
430
431
432
433
434			`doc`
435
436
437			`spirit:library="Testbench"`
438			`spirit:name="toolflow"`
439			`spirit:version="documentation"/>`
440
441			`:Documentation:`
442			`Verilog`
443
444
445
446
447
448
449
450
451
452
453
454
455			`int_o`
456			`wire`
457			`out`
458
459
460
461
462
463			`biu_wr_strobe`
464			`wire`
465			`out`
466
467
468
469
470
471
472			`jsp_data_out`
473			`reg`
474			`out70`
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
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496