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reg actual;
reg [31:0] d;
 
parameter       EXTEST=4'b0000;
parameter       SAMPLE=4'b0001;
parameter       HIGHZ_MODE=4'b0010;
parameter       CHIP_ID_ACCESS=4'b0011;
parameter       CLAMP=4'b1000;
parameter       RPC_DATA=4'b1010;
parameter       RPC_ADD=4'b1001;
parameter       BYPASS=4'b1111;
parameter       INST_RETURN=4'b1101;
 
initial
begin
$display("              ");
$display("              ===================================================");
$display("              Test Start");
$display("              ===================================================");
$display("              ");
test.cg.next(2);
test.jtag_model.enable_tclk;
test.cg.next(20);
fork
begin
test.cg.next(20);
test.mask_jsp_data_out = 8'hff;
test.cg.next(20);
 
while (test.biu_wr_strobe != 1'b1) test.cg.next(1);
test.mask_jsp_data_out = 8'h00;
while (test.biu_wr_strobe != 1'b0) test.cg.next(1);
test.exp_jsp_data_out = 8'hff;
test.mask_jsp_data_out = 8'hff;
 
 
while (test.biu_wr_strobe != 1'b1) test.cg.next(1);
test.mask_jsp_data_out = 8'h00;
while (test.biu_wr_strobe != 1'b0) test.cg.next(1);
test.exp_jsp_data_out = 8'h81;
test.mask_jsp_data_out = 8'hff;
 
 
while (test.biu_wr_strobe != 1'b1) test.cg.next(1);
test.mask_jsp_data_out = 8'h00;
while (test.biu_wr_strobe != 1'b0) test.cg.next(1);
test.exp_jsp_data_out = 8'h18;
test.mask_jsp_data_out = 8'hff;
 
 
while (test.biu_wr_strobe != 1'b1) test.cg.next(1);
test.mask_jsp_data_out = 8'h00;
while (test.biu_wr_strobe != 1'b0) test.cg.next(1);
test.exp_jsp_data_out = 8'hca;
test.mask_jsp_data_out = 8'hff;
 
 
while (test.biu_wr_strobe != 1'b1) test.cg.next(1);
test.mask_jsp_data_out = 8'h00;
while (test.biu_wr_strobe != 1'b0) test.cg.next(1);
test.exp_jsp_data_out = 8'h7e;
test.mask_jsp_data_out = 8'hff;
 
 
while (test.biu_wr_strobe != 1'b1) test.cg.next(1);
test.mask_jsp_data_out = 8'h00;
while (test.biu_wr_strobe != 1'b0) test.cg.next(1);
test.exp_jsp_data_out = 8'h99;
test.mask_jsp_data_out = 8'hff;
 
 
while (test.biu_wr_strobe != 1'b1) test.cg.next(1);
test.mask_jsp_data_out = 8'h00;
while (test.biu_wr_strobe != 1'b0) test.cg.next(1);
test.exp_jsp_data_out = 8'hcc;
test.mask_jsp_data_out = 8'hff;
 
 
while (test.biu_wr_strobe != 1'b1) test.cg.next(1);
test.mask_jsp_data_out = 8'h00;
while (test.biu_wr_strobe != 1'b0) test.cg.next(1);
test.exp_jsp_data_out = 8'h36;
test.mask_jsp_data_out = 8'hff;
 
 
end
 
 
 
begin
test.cg.next(20);
test.jtag_model.enable_trst_n;
test.jtag_model.enable_reset;
test.jtag_model.init;
test.cg.next(10);
test.jtag_model.LoadTapInst(EXTEST,INST_RETURN);
test.cg.next(100);
test.jtag_model.LoadTapInst(CLAMP,INST_RETURN);
 
test.cg.next(100);
test.jtag_model.LoadTapInst(CHIP_ID_ACCESS,INST_RETURN);
test.jtag_model.Shift_Cmp_32(32'ha5a5a5a5,32'h12345678);
 
 
test.cg.next(100);
test.jtag_model.LoadTapInst(RPC_ADD,INST_RETURN);
 
//Shift_Cmp_53(53'h1c000000000000,53'h00000000000000);
 
test.cg.next(5000);
 
 
Shift_Cmp_42(42'b0_11001010_00011000_10000001_11111111_0100_00001       ,42'hx97a7b7c744);
Shift_Cmp_42(42'b0_00110110_11001100_10011001_01111110_0100_00001       ,42'h00000000004);
 
 
test.cg.next(5000);
 
 
 
 
test.cg.next(100);
 
test.jtag_model.LoadTapInst(BYPASS,INST_RETURN);
 
test.cg.next(100);
end
 
 
begin
 
 
test.cg.next(1000);
 
 
fork
  begin
  test.jsp_data_in <= 8'hc7;
  test.jsp_data_in_stb <= 1'b1;
  test.cg.next(2);
  test.jsp_data_in_stb <= 1'b0;
  end
  begin
 
  test.cg.next(1);
  end
join
 
test.cg.next(30);
 
fork
  begin
  test.jsp_data_in <= 8'hb7;
  test.jsp_data_in_stb <= 1'b1;
  test.cg.next(2);
  test.jsp_data_in_stb <= 1'b0;
  end
  begin
 
  test.cg.next(1);
  end
join
 
test.cg.next(30);
 
 
fork
  begin
  test.jsp_data_in <= 8'ha7;
  test.jsp_data_in_stb <= 1'b1;
  test.cg.next(2);
  test.jsp_data_in_stb <= 1'b0;
  end
  begin
 
  test.cg.next(1);
  end
join
 
test.cg.next(30);
 
 
 
fork
  begin
  test.jsp_data_in <= 8'h97;
  test.jsp_data_in_stb <= 1'b1;
  test.cg.next(2);
  test.jsp_data_in_stb <= 1'b0;
  end
  begin
 
  test.cg.next(1);
  end
join
 
test.cg.next(30);
 
 
 
 
 
 
 
end
 
 
 
join
 
 
 
 
test.cg.exit;
end
 
 
 
 
 
 
task automatic  Shift_Cmp_53;    // Initialize boundary register with outputs disabled
                         // This tasks starts at RT_IDLE and ends at SHIFT_DR
 
  parameter [15:0] LENGTH =  53;
 
 
  input [LENGTH:1]  Dataout;
  input [LENGTH:1]  DataExp;
 
  integer i;
 
  reg [LENGTH:1]  DataBack;
 
  begin
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR
    for (i = 1; i <= LENGTH; i = i+1)
       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );
 
   if (DataBack  !== DataExp )
   begin
   test.cg.fail  (" Shift_cmp  receive error  ");
   end
 
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
  end
endtask // ShiftRegister
 
 
task automatic  Shift_Cmp_42;    // Initialize boundary register with outputs disabled
                         // This tasks starts at RT_IDLE and ends at SHIFT_DR
 
  parameter [15:0] LENGTH =  42;
 
 
  input [LENGTH:1]  Dataout;
  input [LENGTH:1]  DataExp;
 
  integer i;
 
  reg [LENGTH:1]  DataBack;
 
  begin
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR
    for (i = 1; i <= LENGTH; i = i+1)
       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );
 
   if (DataBack  !== DataExp )
   begin
   test.cg.fail  (" Shift_cmp  receive error  ");
   end
 
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
  end
endtask // ShiftRegister
 
 
 
 
task automatic  Shift_Cmp_25;    // Initialize boundary register with outputs disabled
                         // This tasks starts at RT_IDLE and ends at SHIFT_DR
 
  parameter [15:0] LENGTH =  25;
 
 
  input [LENGTH:1]  Dataout;
  input [LENGTH:1]  DataExp;
 
  integer i;
 
  reg [LENGTH:1]  DataBack;
 
  begin
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR
    for (i = 1; i <= LENGTH; i = i+1)
       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );
 
   if (DataBack  !== DataExp )
   begin
   test.cg.fail  (" Shift_cmp  receive error  ");
   end
 
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
  end
endtask // ShiftRegister
 
 
 
 
task automatic  Shift_Cmp_34;    // Initialize boundary register with outputs disabled
                         // This tasks starts at RT_IDLE and ends at SHIFT_DR
 
  parameter [15:0] LENGTH =  34;
 
 
  input [LENGTH:1]  Dataout;
  input [LENGTH:1]  DataExp;
 
  integer i;
 
  reg [LENGTH:1]  DataBack;
 
  begin
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR
    for (i = 1; i <= LENGTH; i = i+1)
       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );
 
   if (DataBack  !== DataExp )
   begin
   test.cg.fail  (" Shift_cmp  receive error  ");
   end
 
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
  end
endtask // ShiftRegister
 
 
 
 
 
task automatic  Shift_Cmp_26;    // Initialize boundary register with outputs disabled
                         // This tasks starts at RT_IDLE and ends at SHIFT_DR
 
  parameter [15:0] LENGTH =  26;
 
 
  input [LENGTH:1]  Dataout;
  input [LENGTH:1]  DataExp;
 
  integer i;
 
  reg [LENGTH:1]  DataBack;
 
  begin
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR
    for (i = 1; i <= LENGTH; i = i+1)
       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );
 
   if (DataBack  !== DataExp )
   begin
   test.cg.fail  (" Shift_cmp  receive error  ");
   end
 
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
  end
endtask // ShiftRegister
 
 
 
 
 
 
task automatic  Shift_Cmp_17;    // Initialize boundary register with outputs disabled
                         // This tasks starts at RT_IDLE and ends at SHIFT_DR
 
  parameter [15:0] LENGTH =  17;
 
 
  input [LENGTH:1]  Dataout;
  input [LENGTH:1]  DataExp;
 
  integer i;
 
  reg [LENGTH:1]  DataBack;
 
  begin
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR
    for (i = 1; i <= LENGTH; i = i+1)
       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );
 
   if (DataBack  !== DataExp )
   begin
   test.cg.fail  (" Shift_cmp  receive error  ");
   end
 
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
  end
endtask // ShiftRegister
 
 
 
 
task automatic  Shift_Cmp_9;    // Initialize boundary register with outputs disabled
                         // This tasks starts at RT_IDLE and ends at SHIFT_DR
 
  parameter [15:0] LENGTH =  9;
 
 
  input [LENGTH:1]  Dataout;
  input [LENGTH:1]  DataExp;
 
  integer i;
 
  reg [LENGTH:1]  DataBack;
 
  begin
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR
    for (i = 1; i <= LENGTH; i = i+1)
       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );
 
   if (DataBack  !== DataExp )
   begin
   test.cg.fail  (" Shift_cmp  receive error  ");
   end
 
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
  end
endtask // ShiftRegister
 
 
 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [icarus/] [jfifo/] [test_define] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton	`reg actual;`
2			`reg [31:0] d;`
3
4			`parameter EXTEST=4'b0000;`
5			`parameter SAMPLE=4'b0001;`
6			`parameter HIGHZ_MODE=4'b0010;`
7			`parameter CHIP_ID_ACCESS=4'b0011;`
8			`parameter CLAMP=4'b1000;`
9			`parameter RPC_DATA=4'b1010;`
10			`parameter RPC_ADD=4'b1001;`
11			`parameter BYPASS=4'b1111;`
12			`parameter INST_RETURN=4'b1101;`
13
14			`initial`
15			`begin`
16			`$display(" ");`
17			`$display(" ===================================================");`
18			`$display(" Test Start");`
19			`$display(" ===================================================");`
20			`$display(" ");`
21			`test.cg.next(2);`
22			`test.jtag_model.enable_tclk;`
23			`test.cg.next(20);`
24			`fork`
25			`begin`
26			`test.cg.next(20);`
27			`test.mask_jsp_data_out = 8'hff;`
28			`test.cg.next(20);`
29
30			`while (test.biu_wr_strobe != 1'b1) test.cg.next(1);`
31			`test.mask_jsp_data_out = 8'h00;`
32			`while (test.biu_wr_strobe != 1'b0) test.cg.next(1);`
33			`test.exp_jsp_data_out = 8'hff;`
34			`test.mask_jsp_data_out = 8'hff;`
35
36
37			`while (test.biu_wr_strobe != 1'b1) test.cg.next(1);`
38			`test.mask_jsp_data_out = 8'h00;`
39			`while (test.biu_wr_strobe != 1'b0) test.cg.next(1);`
40			`test.exp_jsp_data_out = 8'h81;`
41			`test.mask_jsp_data_out = 8'hff;`
42
43
44			`while (test.biu_wr_strobe != 1'b1) test.cg.next(1);`
45			`test.mask_jsp_data_out = 8'h00;`
46			`while (test.biu_wr_strobe != 1'b0) test.cg.next(1);`
47			`test.exp_jsp_data_out = 8'h18;`
48			`test.mask_jsp_data_out = 8'hff;`
49
50
51			`while (test.biu_wr_strobe != 1'b1) test.cg.next(1);`
52			`test.mask_jsp_data_out = 8'h00;`
53			`while (test.biu_wr_strobe != 1'b0) test.cg.next(1);`
54			`test.exp_jsp_data_out = 8'hca;`
55			`test.mask_jsp_data_out = 8'hff;`
56
57
58			`while (test.biu_wr_strobe != 1'b1) test.cg.next(1);`
59			`test.mask_jsp_data_out = 8'h00;`
60			`while (test.biu_wr_strobe != 1'b0) test.cg.next(1);`
61			`test.exp_jsp_data_out = 8'h7e;`
62			`test.mask_jsp_data_out = 8'hff;`
63
64
65			`while (test.biu_wr_strobe != 1'b1) test.cg.next(1);`
66			`test.mask_jsp_data_out = 8'h00;`
67			`while (test.biu_wr_strobe != 1'b0) test.cg.next(1);`
68			`test.exp_jsp_data_out = 8'h99;`
69			`test.mask_jsp_data_out = 8'hff;`
70
71
72			`while (test.biu_wr_strobe != 1'b1) test.cg.next(1);`
73			`test.mask_jsp_data_out = 8'h00;`
74			`while (test.biu_wr_strobe != 1'b0) test.cg.next(1);`
75			`test.exp_jsp_data_out = 8'hcc;`
76			`test.mask_jsp_data_out = 8'hff;`
77
78
79			`while (test.biu_wr_strobe != 1'b1) test.cg.next(1);`
80			`test.mask_jsp_data_out = 8'h00;`
81			`while (test.biu_wr_strobe != 1'b0) test.cg.next(1);`
82			`test.exp_jsp_data_out = 8'h36;`
83			`test.mask_jsp_data_out = 8'hff;`
84
85
86			`end`
87
88
89
90			`begin`
91			`test.cg.next(20);`
92			`test.jtag_model.enable_trst_n;`
93			`test.jtag_model.enable_reset;`
94			`test.jtag_model.init;`
95			`test.cg.next(10);`
96			`test.jtag_model.LoadTapInst(EXTEST,INST_RETURN);`
97			`test.cg.next(100);`
98			`test.jtag_model.LoadTapInst(CLAMP,INST_RETURN);`
99
100			`test.cg.next(100);`
101			`test.jtag_model.LoadTapInst(CHIP_ID_ACCESS,INST_RETURN);`
102			`test.jtag_model.Shift_Cmp_32(32'ha5a5a5a5,32'h12345678);`
103
104
105			`test.cg.next(100);`
106			`test.jtag_model.LoadTapInst(RPC_ADD,INST_RETURN);`
107
108			`//Shift_Cmp_53(53'h1c000000000000,53'h00000000000000);`
109
110			`test.cg.next(5000);`
111
112
113			`Shift_Cmp_42(42'b0_11001010_00011000_10000001_11111111_0100_00001 ,42'hx97a7b7c744);`
114			`Shift_Cmp_42(42'b0_00110110_11001100_10011001_01111110_0100_00001 ,42'h00000000004);`
115
116
117			`test.cg.next(5000);`
118
119
120
121
122			`test.cg.next(100);`
123
124			`test.jtag_model.LoadTapInst(BYPASS,INST_RETURN);`
125
126			`test.cg.next(100);`
127			`end`
128
129
130			`begin`
131
132
133			`test.cg.next(1000);`
134
135
136			`fork`
137			`begin`
138			`test.jsp_data_in <= 8'hc7;`
139			`test.jsp_data_in_stb <= 1'b1;`
140			`test.cg.next(2);`
141			`test.jsp_data_in_stb <= 1'b0;`
142			`end`
143			`begin`
144
145			`test.cg.next(1);`
146			`end`
147			`join`
148
149			`test.cg.next(30);`
150
151			`fork`
152			`begin`
153			`test.jsp_data_in <= 8'hb7;`
154			`test.jsp_data_in_stb <= 1'b1;`
155			`test.cg.next(2);`
156			`test.jsp_data_in_stb <= 1'b0;`
157			`end`
158			`begin`
159
160			`test.cg.next(1);`
161			`end`
162			`join`
163
164			`test.cg.next(30);`
165
166
167			`fork`
168			`begin`
169			`test.jsp_data_in <= 8'ha7;`
170			`test.jsp_data_in_stb <= 1'b1;`
171			`test.cg.next(2);`
172			`test.jsp_data_in_stb <= 1'b0;`
173			`end`
174			`begin`
175
176			`test.cg.next(1);`
177			`end`
178			`join`
179
180			`test.cg.next(30);`
181
182
183
184			`fork`
185			`begin`
186			`test.jsp_data_in <= 8'h97;`
187			`test.jsp_data_in_stb <= 1'b1;`
188			`test.cg.next(2);`
189			`test.jsp_data_in_stb <= 1'b0;`
190			`end`
191			`begin`
192
193			`test.cg.next(1);`
194			`end`
195			`join`
196
197			`test.cg.next(30);`
198
199
200
201
202
203
204
205			`end`
206
207
208
209			`join`
210
211
212
213
214			`test.cg.exit;`
215			`end`
216
217
218
219
220
221
222			`task automatic Shift_Cmp_53; // Initialize boundary register with outputs disabled`
223			`// This tasks starts at RT_IDLE and ends at SHIFT_DR`
224
225			`parameter [15:0] LENGTH = 53;`
226
227
228			`input [LENGTH:1] Dataout;`
229			`input [LENGTH:1] DataExp;`
230
231			`integer i;`
232
233			`reg [LENGTH:1] DataBack;`
234
235			`begin`
236			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR`
237			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR`
238			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR`
239			`for (i = 1; i <= LENGTH; i = i+1)`
240			`test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);`
241			`$display ("%t %m Shift_data_register wr-%h exp-%h rd-%h ",$realtime,Dataout,DataExp,DataBack );`
242
243			`if (DataBack !== DataExp )`
244			`begin`
245			`test.cg.fail (" Shift_cmp receive error ");`
246			`end`
247
248			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR`
249			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE`
250			`end`
251			`endtask // ShiftRegister`
252
253
254			`task automatic Shift_Cmp_42; // Initialize boundary register with outputs disabled`
255			`// This tasks starts at RT_IDLE and ends at SHIFT_DR`
256
257			`parameter [15:0] LENGTH = 42;`
258
259
260			`input [LENGTH:1] Dataout;`
261			`input [LENGTH:1] DataExp;`
262
263			`integer i;`
264
265			`reg [LENGTH:1] DataBack;`
266
267			`begin`
268			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR`
269			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR`
270			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR`
271			`for (i = 1; i <= LENGTH; i = i+1)`
272			`test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);`
273			`$display ("%t %m Shift_data_register wr-%h exp-%h rd-%h ",$realtime,Dataout,DataExp,DataBack );`
274
275			`if (DataBack !== DataExp )`
276			`begin`
277			`test.cg.fail (" Shift_cmp receive error ");`
278			`end`
279
280			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR`
281			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE`
282			`end`
283			`endtask // ShiftRegister`
284
285
286
287
288			`task automatic Shift_Cmp_25; // Initialize boundary register with outputs disabled`
289			`// This tasks starts at RT_IDLE and ends at SHIFT_DR`
290
291			`parameter [15:0] LENGTH = 25;`
292
293
294			`input [LENGTH:1] Dataout;`
295			`input [LENGTH:1] DataExp;`
296
297			`integer i;`
298
299			`reg [LENGTH:1] DataBack;`
300
301			`begin`
302			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR`
303			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR`
304			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR`
305			`for (i = 1; i <= LENGTH; i = i+1)`
306			`test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);`
307			`$display ("%t %m Shift_data_register wr-%h exp-%h rd-%h ",$realtime,Dataout,DataExp,DataBack );`
308
309			`if (DataBack !== DataExp )`
310			`begin`
311			`test.cg.fail (" Shift_cmp receive error ");`
312			`end`
313
314			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR`
315			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE`
316			`end`
317			`endtask // ShiftRegister`
318
319
320
321
322			`task automatic Shift_Cmp_34; // Initialize boundary register with outputs disabled`
323			`// This tasks starts at RT_IDLE and ends at SHIFT_DR`
324
325			`parameter [15:0] LENGTH = 34;`
326
327
328			`input [LENGTH:1] Dataout;`
329			`input [LENGTH:1] DataExp;`
330
331			`integer i;`
332
333			`reg [LENGTH:1] DataBack;`
334
335			`begin`
336			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR`
337			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR`
338			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR`
339			`for (i = 1; i <= LENGTH; i = i+1)`
340			`test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);`
341			`$display ("%t %m Shift_data_register wr-%h exp-%h rd-%h ",$realtime,Dataout,DataExp,DataBack );`
342
343			`if (DataBack !== DataExp )`
344			`begin`
345			`test.cg.fail (" Shift_cmp receive error ");`
346			`end`
347
348			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR`
349			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE`
350			`end`
351			`endtask // ShiftRegister`
352
353
354
355
356
357			`task automatic Shift_Cmp_26; // Initialize boundary register with outputs disabled`
358			`// This tasks starts at RT_IDLE and ends at SHIFT_DR`
359
360			`parameter [15:0] LENGTH = 26;`
361
362
363			`input [LENGTH:1] Dataout;`
364			`input [LENGTH:1] DataExp;`
365
366			`integer i;`
367
368			`reg [LENGTH:1] DataBack;`
369
370			`begin`
371			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR`
372			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR`
373			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR`
374			`for (i = 1; i <= LENGTH; i = i+1)`
375			`test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);`
376			`$display ("%t %m Shift_data_register wr-%h exp-%h rd-%h ",$realtime,Dataout,DataExp,DataBack );`
377
378			`if (DataBack !== DataExp )`
379			`begin`
380			`test.cg.fail (" Shift_cmp receive error ");`
381			`end`
382
383			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR`
384			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE`
385			`end`
386			`endtask // ShiftRegister`
387
388
389
390
391
392
393			`task automatic Shift_Cmp_17; // Initialize boundary register with outputs disabled`
394			`// This tasks starts at RT_IDLE and ends at SHIFT_DR`
395
396			`parameter [15:0] LENGTH = 17;`
397
398
399			`input [LENGTH:1] Dataout;`
400			`input [LENGTH:1] DataExp;`
401
402			`integer i;`
403
404			`reg [LENGTH:1] DataBack;`
405
406			`begin`
407			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR`
408			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR`
409			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR`
410			`for (i = 1; i <= LENGTH; i = i+1)`
411			`test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);`
412			`$display ("%t %m Shift_data_register wr-%h exp-%h rd-%h ",$realtime,Dataout,DataExp,DataBack );`
413
414			`if (DataBack !== DataExp )`
415			`begin`
416			`test.cg.fail (" Shift_cmp receive error ");`
417			`end`
418
419			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR`
420			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE`
421			`end`
422			`endtask // ShiftRegister`
423
424
425
426
427			`task automatic Shift_Cmp_9; // Initialize boundary register with outputs disabled`
428			`// This tasks starts at RT_IDLE and ends at SHIFT_DR`
429
430			`parameter [15:0] LENGTH = 9;`
431
432
433			`input [LENGTH:1] Dataout;`
434			`input [LENGTH:1] DataExp;`
435
436			`integer i;`
437
438			`reg [LENGTH:1] DataBack;`
439
440			`begin`
441			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR`
442			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR`
443			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR`
444			`for (i = 1; i <= LENGTH; i = i+1)`
445			`test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);`
446			`$display ("%t %m Shift_data_register wr-%h exp-%h rd-%h ",$realtime,Dataout,DataExp,DataBack );`
447
448			`if (DataBack !== DataExp )`
449			`begin`
450			`test.cg.fail (" Shift_cmp receive error ");`
451			`end`
452
453			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR`
454			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE`
455			`end`
456			`endtask // ShiftRegister`
457
458
459
460
461
462
463