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reg actual;
reg [31:0] d;
 
parameter       EXTEST=4'b0000;
parameter       SAMPLE=4'b0001;
parameter       HIGHZ_MODE=4'b0010;
parameter       CHIP_ID_ACCESS=4'b0011;
parameter       CLAMP=4'b1000;
parameter       RPC_DATA=4'b1010;
parameter       RPC_ADD=4'b1001;
parameter       BYPASS=4'b1111;
parameter       INST_RETURN=4'b1101;
 
initial
begin
$display("              ");
$display("              ===================================================");
$display("              Test Start");
$display("              ===================================================");
$display("              ");
test.cg.next(2);
test.jtag_model.enable_tclk;
test.cg.next(20);
fork
begin
test.cg.next(20);
test.jtag_model.enable_trst_n;
test.jtag_model.enable_reset;
test.jtag_model.init;
test.cg.next(10);
test.jtag_model.LoadTapInst(EXTEST,INST_RETURN);
test.cg.next(100);
test.jtag_model.LoadTapInst(CLAMP,INST_RETURN);
 
 
test.cg.next(100);
test.jtag_model.LoadTapInst(CHIP_ID_ACCESS,INST_RETURN);
test.jtag_model.Shift_Cmp_32(32'ha5a5a5a5,32'h12345678);
 
 
test.cg.next(100);
test.jtag_model.LoadTapInst(RPC_ADD,INST_RETURN);
 
Shift_Cmp_53(53'h1c000000000000,53'h00000000000000);
 
test.cg.next(5000);
 
 
Shift_Cmp_42(42'b0_11001010_00011000_10000001_11111111_0100_00001       ,42'hxc7c7c7c748);
Shift_Cmp_42(42'b0_00110110_11001100_10011001_01111110_0100_00001       ,42'h00000000004);
 
 
test.cg.next(5000);
 
 
 
 
test.cg.next(100);
 
test.jtag_model.LoadTapInst(BYPASS,INST_RETURN);
 
test.cg.next(100);
end
 
 
begin
 
test.cg.next(100);
 
test.i_wb_master.wb_write(32'h00000000,4'hf,32'hc7c7c7c7 );
test.i_wb_master.wb_write(32'h00000000,4'hf,32'hc7c7c7c7 );
test.i_wb_master.wb_write(32'h00000000,4'hf,32'hc7c7c7c7 );
test.i_wb_master.wb_write(32'h00000000,4'hf,32'hc7c7c7c7 );
 
 
 
test.cg.next(10000);
 
test.i_wb_master.wb_read(32'h00000000,d );
test.cg.next(100);
 
test.i_wb_master.wb_read(32'h00000000,d );
test.cg.next(100);
 
test.i_wb_master.wb_read(32'h00000000,d );
test.cg.next(100);
 
test.i_wb_master.wb_read(32'h00000000,d );
test.cg.next(100);
 
test.i_wb_master.wb_read(32'h00000000,d );
test.cg.next(100);
 
test.i_wb_master.wb_read(32'h00000000,d );
test.cg.next(100);
 
test.i_wb_master.wb_read(32'h00000000,d );
test.cg.next(100);
 
test.i_wb_master.wb_read(32'h00000000,d );
test.cg.next(100);
 
 
 
 
 
 
 
 
 
 
end
 
 
 
join
 
 
 
 
test.cg.exit;
end
 
 
 
 
 
 
task automatic  Shift_Cmp_53;    // Initialize boundary register with outputs disabled
                         // This tasks starts at RT_IDLE and ends at SHIFT_DR
 
  parameter [15:0] LENGTH =  53;
 
 
  input [LENGTH:1]  Dataout;
  input [LENGTH:1]  DataExp;
 
  integer i;
 
  reg [LENGTH:1]  DataBack;
 
  begin
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR
    for (i = 1; i <= LENGTH; i = i+1)
       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );
 
   if (DataBack  !== DataExp )
   begin
   test.cg.fail  (" Shift_cmp  receive error  ");
   end
 
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
  end
endtask // ShiftRegister
 
 
task automatic  Shift_Cmp_42;    // Initialize boundary register with outputs disabled
                         // This tasks starts at RT_IDLE and ends at SHIFT_DR
 
  parameter [15:0] LENGTH =  42;
 
 
  input [LENGTH:1]  Dataout;
  input [LENGTH:1]  DataExp;
 
  integer i;
 
  reg [LENGTH:1]  DataBack;
 
  begin
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR
    for (i = 1; i <= LENGTH; i = i+1)
       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );
 
   if (DataBack  !== DataExp )
   begin
   test.cg.fail  (" Shift_cmp  receive error  ");
   end
 
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
  end
endtask // ShiftRegister
 
 
 
 
task automatic  Shift_Cmp_25;    // Initialize boundary register with outputs disabled
                         // This tasks starts at RT_IDLE and ends at SHIFT_DR
 
  parameter [15:0] LENGTH =  25;
 
 
  input [LENGTH:1]  Dataout;
  input [LENGTH:1]  DataExp;
 
  integer i;
 
  reg [LENGTH:1]  DataBack;
 
  begin
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR
    for (i = 1; i <= LENGTH; i = i+1)
       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );
 
   if (DataBack  !== DataExp )
   begin
   test.cg.fail  (" Shift_cmp  receive error  ");
   end
 
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
  end
endtask // ShiftRegister
 
 
 
 
task automatic  Shift_Cmp_34;    // Initialize boundary register with outputs disabled
                         // This tasks starts at RT_IDLE and ends at SHIFT_DR
 
  parameter [15:0] LENGTH =  34;
 
 
  input [LENGTH:1]  Dataout;
  input [LENGTH:1]  DataExp;
 
  integer i;
 
  reg [LENGTH:1]  DataBack;
 
  begin
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR
    for (i = 1; i <= LENGTH; i = i+1)
       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );
 
   if (DataBack  !== DataExp )
   begin
   test.cg.fail  (" Shift_cmp  receive error  ");
   end
 
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
  end
endtask // ShiftRegister
 
 
 
 
 
task automatic  Shift_Cmp_26;    // Initialize boundary register with outputs disabled
                         // This tasks starts at RT_IDLE and ends at SHIFT_DR
 
  parameter [15:0] LENGTH =  26;
 
 
  input [LENGTH:1]  Dataout;
  input [LENGTH:1]  DataExp;
 
  integer i;
 
  reg [LENGTH:1]  DataBack;
 
  begin
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR
    for (i = 1; i <= LENGTH; i = i+1)
       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );
 
   if (DataBack  !== DataExp )
   begin
   test.cg.fail  (" Shift_cmp  receive error  ");
   end
 
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
  end
endtask // ShiftRegister
 
 
 
 
 
 
task automatic  Shift_Cmp_17;    // Initialize boundary register with outputs disabled
                         // This tasks starts at RT_IDLE and ends at SHIFT_DR
 
  parameter [15:0] LENGTH =  17;
 
 
  input [LENGTH:1]  Dataout;
  input [LENGTH:1]  DataExp;
 
  integer i;
 
  reg [LENGTH:1]  DataBack;
 
  begin
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR
    for (i = 1; i <= LENGTH; i = i+1)
       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );
 
   if (DataBack  !== DataExp )
   begin
   test.cg.fail  (" Shift_cmp  receive error  ");
   end
 
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
  end
endtask // ShiftRegister
 
 
 
 
task automatic  Shift_Cmp_9;    // Initialize boundary register with outputs disabled
                         // This tasks starts at RT_IDLE and ends at SHIFT_DR
 
  parameter [15:0] LENGTH =  9;
 
 
  input [LENGTH:1]  Dataout;
  input [LENGTH:1]  DataExp;
 
  integer i;
 
  reg [LENGTH:1]  DataBack;
 
  begin
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR
    for (i = 1; i <= LENGTH; i = i+1)
       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );
 
   if (DataBack  !== DataExp )
   begin
   test.cg.fail  (" Shift_cmp  receive error  ");
   end
 
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
  end
endtask // ShiftRegister
 
 
 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [icarus/] [jsp/] [test_define] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton	`reg actual;`
2			`reg [31:0] d;`
3
4			`parameter EXTEST=4'b0000;`
5			`parameter SAMPLE=4'b0001;`
6			`parameter HIGHZ_MODE=4'b0010;`
7			`parameter CHIP_ID_ACCESS=4'b0011;`
8			`parameter CLAMP=4'b1000;`
9			`parameter RPC_DATA=4'b1010;`
10			`parameter RPC_ADD=4'b1001;`
11			`parameter BYPASS=4'b1111;`
12			`parameter INST_RETURN=4'b1101;`
13
14			`initial`
15			`begin`
16			`$display(" ");`
17			`$display(" ===================================================");`
18			`$display(" Test Start");`
19			`$display(" ===================================================");`
20			`$display(" ");`
21			`test.cg.next(2);`
22			`test.jtag_model.enable_tclk;`
23			`test.cg.next(20);`
24			`fork`
25			`begin`
26			`test.cg.next(20);`
27			`test.jtag_model.enable_trst_n;`
28			`test.jtag_model.enable_reset;`
29			`test.jtag_model.init;`
30			`test.cg.next(10);`
31			`test.jtag_model.LoadTapInst(EXTEST,INST_RETURN);`
32			`test.cg.next(100);`
33			`test.jtag_model.LoadTapInst(CLAMP,INST_RETURN);`
34
35
36			`test.cg.next(100);`
37			`test.jtag_model.LoadTapInst(CHIP_ID_ACCESS,INST_RETURN);`
38			`test.jtag_model.Shift_Cmp_32(32'ha5a5a5a5,32'h12345678);`
39
40
41			`test.cg.next(100);`
42			`test.jtag_model.LoadTapInst(RPC_ADD,INST_RETURN);`
43
44			`Shift_Cmp_53(53'h1c000000000000,53'h00000000000000);`
45
46			`test.cg.next(5000);`
47
48
49			`Shift_Cmp_42(42'b0_11001010_00011000_10000001_11111111_0100_00001 ,42'hxc7c7c7c748);`
50			`Shift_Cmp_42(42'b0_00110110_11001100_10011001_01111110_0100_00001 ,42'h00000000004);`
51
52
53			`test.cg.next(5000);`
54
55
56
57
58			`test.cg.next(100);`
59
60			`test.jtag_model.LoadTapInst(BYPASS,INST_RETURN);`
61
62			`test.cg.next(100);`
63			`end`
64
65
66			`begin`
67
68			`test.cg.next(100);`
69
70			`test.i_wb_master.wb_write(32'h00000000,4'hf,32'hc7c7c7c7 );`
71			`test.i_wb_master.wb_write(32'h00000000,4'hf,32'hc7c7c7c7 );`
72			`test.i_wb_master.wb_write(32'h00000000,4'hf,32'hc7c7c7c7 );`
73			`test.i_wb_master.wb_write(32'h00000000,4'hf,32'hc7c7c7c7 );`
74
75
76
77			`test.cg.next(10000);`
78
79			`test.i_wb_master.wb_read(32'h00000000,d );`
80			`test.cg.next(100);`
81
82			`test.i_wb_master.wb_read(32'h00000000,d );`
83			`test.cg.next(100);`
84
85			`test.i_wb_master.wb_read(32'h00000000,d );`
86			`test.cg.next(100);`
87
88			`test.i_wb_master.wb_read(32'h00000000,d );`
89			`test.cg.next(100);`
90
91			`test.i_wb_master.wb_read(32'h00000000,d );`
92			`test.cg.next(100);`
93
94			`test.i_wb_master.wb_read(32'h00000000,d );`
95			`test.cg.next(100);`
96
97			`test.i_wb_master.wb_read(32'h00000000,d );`
98			`test.cg.next(100);`
99
100			`test.i_wb_master.wb_read(32'h00000000,d );`
101			`test.cg.next(100);`
102
103
104
105
106
107
108
109
110
111
112			`end`
113
114
115
116			`join`
117
118
119
120
121			`test.cg.exit;`
122			`end`
123
124
125
126
127
128
129			`task automatic Shift_Cmp_53; // Initialize boundary register with outputs disabled`
130			`// This tasks starts at RT_IDLE and ends at SHIFT_DR`
131
132			`parameter [15:0] LENGTH = 53;`
133
134
135			`input [LENGTH:1] Dataout;`
136			`input [LENGTH:1] DataExp;`
137
138			`integer i;`
139
140			`reg [LENGTH:1] DataBack;`
141
142			`begin`
143			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR`
144			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR`
145			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR`
146			`for (i = 1; i <= LENGTH; i = i+1)`
147			`test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);`
148			`$display ("%t %m Shift_data_register wr-%h exp-%h rd-%h ",$realtime,Dataout,DataExp,DataBack );`
149
150			`if (DataBack !== DataExp )`
151			`begin`
152			`test.cg.fail (" Shift_cmp receive error ");`
153			`end`
154
155			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR`
156			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE`
157			`end`
158			`endtask // ShiftRegister`
159
160
161			`task automatic Shift_Cmp_42; // Initialize boundary register with outputs disabled`
162			`// This tasks starts at RT_IDLE and ends at SHIFT_DR`
163
164			`parameter [15:0] LENGTH = 42;`
165
166
167			`input [LENGTH:1] Dataout;`
168			`input [LENGTH:1] DataExp;`
169
170			`integer i;`
171
172			`reg [LENGTH:1] DataBack;`
173
174			`begin`
175			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR`
176			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR`
177			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR`
178			`for (i = 1; i <= LENGTH; i = i+1)`
179			`test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);`
180			`$display ("%t %m Shift_data_register wr-%h exp-%h rd-%h ",$realtime,Dataout,DataExp,DataBack );`
181
182			`if (DataBack !== DataExp )`
183			`begin`
184			`test.cg.fail (" Shift_cmp receive error ");`
185			`end`
186
187			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR`
188			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE`
189			`end`
190			`endtask // ShiftRegister`
191
192
193
194
195			`task automatic Shift_Cmp_25; // Initialize boundary register with outputs disabled`
196			`// This tasks starts at RT_IDLE and ends at SHIFT_DR`
197
198			`parameter [15:0] LENGTH = 25;`
199
200
201			`input [LENGTH:1] Dataout;`
202			`input [LENGTH:1] DataExp;`
203
204			`integer i;`
205
206			`reg [LENGTH:1] DataBack;`
207
208			`begin`
209			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR`
210			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR`
211			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR`
212			`for (i = 1; i <= LENGTH; i = i+1)`
213			`test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);`
214			`$display ("%t %m Shift_data_register wr-%h exp-%h rd-%h ",$realtime,Dataout,DataExp,DataBack );`
215
216			`if (DataBack !== DataExp )`
217			`begin`
218			`test.cg.fail (" Shift_cmp receive error ");`
219			`end`
220
221			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR`
222			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE`
223			`end`
224			`endtask // ShiftRegister`
225
226
227
228
229			`task automatic Shift_Cmp_34; // Initialize boundary register with outputs disabled`
230			`// This tasks starts at RT_IDLE and ends at SHIFT_DR`
231
232			`parameter [15:0] LENGTH = 34;`
233
234
235			`input [LENGTH:1] Dataout;`
236			`input [LENGTH:1] DataExp;`
237
238			`integer i;`
239
240			`reg [LENGTH:1] DataBack;`
241
242			`begin`
243			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR`
244			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR`
245			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR`
246			`for (i = 1; i <= LENGTH; i = i+1)`
247			`test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);`
248			`$display ("%t %m Shift_data_register wr-%h exp-%h rd-%h ",$realtime,Dataout,DataExp,DataBack );`
249
250			`if (DataBack !== DataExp )`
251			`begin`
252			`test.cg.fail (" Shift_cmp receive error ");`
253			`end`
254
255			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR`
256			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE`
257			`end`
258			`endtask // ShiftRegister`
259
260
261
262
263
264			`task automatic Shift_Cmp_26; // Initialize boundary register with outputs disabled`
265			`// This tasks starts at RT_IDLE and ends at SHIFT_DR`
266
267			`parameter [15:0] LENGTH = 26;`
268
269
270			`input [LENGTH:1] Dataout;`
271			`input [LENGTH:1] DataExp;`
272
273			`integer i;`
274
275			`reg [LENGTH:1] DataBack;`
276
277			`begin`
278			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR`
279			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR`
280			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR`
281			`for (i = 1; i <= LENGTH; i = i+1)`
282			`test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);`
283			`$display ("%t %m Shift_data_register wr-%h exp-%h rd-%h ",$realtime,Dataout,DataExp,DataBack );`
284
285			`if (DataBack !== DataExp )`
286			`begin`
287			`test.cg.fail (" Shift_cmp receive error ");`
288			`end`
289
290			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR`
291			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE`
292			`end`
293			`endtask // ShiftRegister`
294
295
296
297
298
299
300			`task automatic Shift_Cmp_17; // Initialize boundary register with outputs disabled`
301			`// This tasks starts at RT_IDLE and ends at SHIFT_DR`
302
303			`parameter [15:0] LENGTH = 17;`
304
305
306			`input [LENGTH:1] Dataout;`
307			`input [LENGTH:1] DataExp;`
308
309			`integer i;`
310
311			`reg [LENGTH:1] DataBack;`
312
313			`begin`
314			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR`
315			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR`
316			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR`
317			`for (i = 1; i <= LENGTH; i = i+1)`
318			`test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);`
319			`$display ("%t %m Shift_data_register wr-%h exp-%h rd-%h ",$realtime,Dataout,DataExp,DataBack );`
320
321			`if (DataBack !== DataExp )`
322			`begin`
323			`test.cg.fail (" Shift_cmp receive error ");`
324			`end`
325
326			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR`
327			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE`
328			`end`
329			`endtask // ShiftRegister`
330
331
332
333
334			`task automatic Shift_Cmp_9; // Initialize boundary register with outputs disabled`
335			`// This tasks starts at RT_IDLE and ends at SHIFT_DR`
336
337			`parameter [15:0] LENGTH = 9;`
338
339
340			`input [LENGTH:1] Dataout;`
341			`input [LENGTH:1] DataExp;`
342
343			`integer i;`
344
345			`reg [LENGTH:1] DataBack;`
346
347			`begin`
348			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR`
349			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR`
350			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR`
351			`for (i = 1; i <= LENGTH; i = i+1)`
352			`test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);`
353			`$display ("%t %m Shift_data_register wr-%h exp-%h rd-%h ",$realtime,Dataout,DataExp,DataBack );`
354
355			`if (DataBack !== DataExp )`
356			`begin`
357			`test.cg.fail (" Shift_cmp receive error ");`
358			`end`
359
360			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR`
361			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE`
362			`end`
363			`endtask // ShiftRegister`
364
365
366
367
368
369
370