OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [icarus/] [wb/] [wave.sav] - Blame information for rev 131

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 131 jt_eaton
[*]
2
[*] GTKWave Analyzer v3.3.40 (w)1999-2012 BSI
3
[*] Thu Aug 29 03:07:57 2013
4
[*]
5
[dumpfile] "/home/johne/Desktop/socgen/work/opencores.org__adv_debug_sys/Hardware/adv_dbg_if/sim/icarus/wb/TestBench.vcd"
6
[dumpfile_mtime] "Thu Aug 29 03:06:31 2013"
7
[dumpfile_size] 636696
8
[savefile] "/home/johne/Desktop/socgen/projects/opencores.org/adv_debug_sys/Hardware/adv_dbg_if/sim/icarus/wb/wave.sav"
9
[timestart] 0
10
[size] 1613 1011
11
[pos] 528 24
12
*-17.000000 127740 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
13
[treeopen] TB.
14
[treeopen] TB.test.
15
[treeopen] TB.test.dut.
16
[treeopen] TB.test.jtag_tap.
17
[treeopen] TB.test.wb_ram.
18
[sst_width] 331
19
[signals_width] 398
20
[sst_expanded] 1
21
[sst_vpaned_height] 330
22
@200
23
-
24
@28
25
TB.test.jtag_clk
26
TB.test.test_logic_reset_o
27
TB.test.shift_dr_o
28
@800028
29
TB.test.tdo_i[1:0]
30
@1001200
31
-group_end
32
@28
33
TB.test.debug_select_i
34
TB.test.update_dr_clk_o
35
TB.test.tdi_o
36
TB.test.capture_dr_i
37
TB.test.shift_dr_i
38
TB.test.update_dr_i
39
TB.test.shift_dr_i
40
@820
41
TB.test.jtag_tap.inst_string[127:0]
42
TB.test.jtag_tap.tap_string[127:0]
43
@22
44
TB.test.dut.input_shift_reg[52:0]
45
@28
46
TB.test.dut.module_id_in[1:0]
47
TB.test.dut.module_id_reg[1:0]
48
@22
49
TB.test.dut.module_inhibit[3:0]
50
TB.test.dut.module_selects[3:0]
51
@28
52
TB.test.dut.select_cmd
53
TB.test.dut.select_inhibit
54
TB.test.dut.shift_dr_i
55
TB.test.dut.tdi_i
56
TB.test.wb_ack_i
57
@22
58
TB.test.wb_adr_o[31:0]
59
@28
60
TB.test.wb_bte_o[1:0]
61
TB.test.wb_cab_o
62
TB.test.wb_clk_i
63
TB.test.wb_cti_o[2:0]
64
TB.test.wb_cyc_o
65
@22
66
TB.test.wb_dat_i[31:0]
67
TB.test.wb_dat_o[31:0]
68
@28
69
TB.test.wb_err_i
70
TB.test.wb_rst_i
71
@22
72
TB.test.wb_sel_o[3:0]
73
@28
74
TB.test.wb_ram.clk_i
75
TB.test.wb_ram.rst_i
76
@22
77
TB.test.wb_ram.adr_i[31:0]
78
@28
79
TB.test.wb_ram.cyc_i
80
@22
81
TB.test.wb_ram.dat_i[31:0]
82
TB.test.wb_ram.dat_o[31:0]
83
TB.test.wb_ram.sel_i[3:0]
84
@28
85
TB.test.wb_ram.sram_wr
86
TB.test.wb_ram.stb_i
87
TB.test.wb_ram.waitst
88
@29
89
TB.test.wb_ram.we_i
90
[pattern_trace] 1
91
[pattern_trace] 0

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.