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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [verilog/] [tb.jfifo_sync] - Blame information for rev 131

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Line No. Rev Author Line
1 131 jt_eaton
assign wb_clk_i   = clk;
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assign wb_jsp_dat_i = {jsp_data_in,jsp_data_in,jsp_data_in,jsp_data_in};
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assign wb_jsp_stb_i = jsp_data_in_stb;
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reg [7:0]  jsp_data_in ;
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reg        jsp_data_in_stb ;
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reg [7:0]  exp_jsp_data_out ;
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reg [7:0]  mask_jsp_data_out;
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io_probe_in
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 #(.MESG         ("jsp_data_out Error"),
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   .WIDTH        (8)
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  )
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rdata_tpb
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  (
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  .clk            (  clk        ),
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  .expected_value (  exp_jsp_data_out  ),
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  .mask           (  mask_jsp_data_out ),
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  .signal         (  jsp_data_out      )
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  );
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initial
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begin
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exp_jsp_data_out  <= 8'h00;
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mask_jsp_data_out <= 8'h00;
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jsp_data_in       <= 8'h00;
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jsp_data_in_stb   <= 1'b0;
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end
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assign rst_i          = test_logic_reset_o;
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assign tdo_i[0]       = tdo_o;
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assign tdo_i[1]       = 1'b0;
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assign bsr_tdo_i      = 1'b0;
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assign tck_i          = syn_clk;
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assign capture_dr_i   = syn_capture_dr;
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assign shift_dr_i     = syn_shift_dr;
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assign update_dr_i    = syn_update_dr;
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assign debug_select_i = syn_select[0];
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assign tdi_i          = syn_tdi_o;

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