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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [verilog/] [tb.jfifo_sync] - Blame information for rev 133

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Line No. Rev Author Line
1 131 jt_eaton
assign wb_clk_i   = clk;
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assign wb_jsp_dat_i = {jsp_data_in,jsp_data_in,jsp_data_in,jsp_data_in};
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assign wb_jsp_stb_i = jsp_data_in_stb;
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reg [7:0]  jsp_data_in ;
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reg        jsp_data_in_stb ;
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initial
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begin
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exp_jsp_data_out  <= 8'h00;
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mask_jsp_data_out <= 8'h00;
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jsp_data_in       <= 8'h00;
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jsp_data_in_stb   <= 1'b0;
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end
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assign rst_i          = test_logic_reset_o;
25 133 jt_eaton
assign tdo_i          = tdo_o;
26 131 jt_eaton
assign bsr_tdo_i      = 1'b0;
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assign tck_i          = syn_clk;
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assign capture_dr_i   = syn_capture_dr;
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assign shift_dr_i     = syn_shift_dr;
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assign update_dr_i    = syn_update_dr;
31 133 jt_eaton
assign debug_select_i = syn_select;
32 131 jt_eaton
assign tdi_i          = syn_tdi_o;

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