URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [verilog/] [tb.jsp] - Blame information for rev 133

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assign wb_clk_i   = clk;
assign wb_rst_i   = reset;
 
assign wb_jsp_bte_i   = 2'b00;
assign wb_jsp_cti_i   = 3'b000;
assign wb_jsp_cab_i   = 1'b0;
assign tck_i          = jtag_clk;
assign capture_dr_i   = capture_dr_o;
assign shift_dr_i     = shift_dr_o;
assign update_dr_i    = update_dr_o;
assign debug_select_i = select_o;
assign rst_i          = test_logic_reset_o;
assign tdo_i          = tdo_o;
assign bsr_tdo_i      = 1'b0;
assign tdi_i          = tdi_o;
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton	`assign wb_clk_i = clk;`
2			`assign wb_rst_i = reset;`
3
4			`assign wb_jsp_bte_i = 2'b00;`
5			`assign wb_jsp_cti_i = 3'b000;`
6			`assign wb_jsp_cab_i = 1'b0;`
7			`assign tck_i = jtag_clk;`
8			`assign capture_dr_i = capture_dr_o;`
9			`assign shift_dr_i = shift_dr_o;`
10			`assign update_dr_i = update_dr_o;`
11	133	jt_eaton	`assign debug_select_i = select_o;`
12	131	jt_eaton	`assign rst_i = test_logic_reset_o;`
13	133	jt_eaton	`assign tdo_i = tdo_o;`
14	131	jt_eaton	`assign bsr_tdo_i = 1'b0;`
15			`assign tdi_i = tdi_o;`
16
17

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [verilog/] [tb.jsp] - Blame information for rev 133