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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [xml/] [adv_dbg_if_cpu0_tb.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
adv_debug_sys
adv_dbg_if
cpu0_tb
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top.tb.cpu0
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 

 
 
 
 
 
 
 


    JTAG_MODEL_DIVCNT     4'h4
    JTAG_MODEL_SIZE       4

 
       
 
              
              Params
              
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="cpu0_dut.params"/>
             
              
 
 
              
              Bfm
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="bfm.design"/>
              
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 
 

 
 
 
 
 

 
 
 
 
   
      fs-common
 
 
 
 
      
        
        ../verilog/tb.cpu0
        verilogSource
        fragment
      
 
 
 
 
 
 
 
 
   
 
 
 
 
 
   
      fs-sim
 
 
      
        
        ../verilog/tb.ext
        verilogSource
        fragment
      
 
 
 
 
      
        
        ../verilog/common/top.tb.cpu0
        verilogSourcemodule
      
 
 
 
 
   
 
 
   
      fs-lint
      
        
        ../verilog/common/top.tb.cpu0
        verilogSourcemodule
      
 
 
   
 
 
 
 
 

 
 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [xml/] [adv_dbg_if_cpu0_tb.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`adv_debug_sys`
14			`adv_dbg_if`
15			`cpu0_tb`
16
17
18
19
20
21
22
23
24
25			`gen_verilog`
26			`104.0`
27			`none`
28			`common`
29			`./tools/verilog/gen_verilog`
30
31
32			`destination`
33	133	jt_eaton	`top.tb.cpu0`
34	131	jt_eaton
35
36			`dest_dir`
37			`../verilog`
38
39
40			`top`
41
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57			`JTAG_MODEL_DIVCNT 4'h4`
58			`JTAG_MODEL_SIZE 4`
59
60
61
62
63
64			`Params`
65
66
67			`spirit:library="adv_debug_sys"`
68			`spirit:name="adv_dbg_if"`
69			`spirit:version="cpu0_dut.params"/>`
70
71
72
73
74
75			`Bfm`
76
77			`spirit:library="adv_debug_sys"`
78			`spirit:name="adv_dbg_if"`
79			`spirit:version="bfm.design"/>`
80
81
82
83
84			`icarus`
85
86
87			`spirit:library="Testbench"`
88			`spirit:name="toolflow"`
89			`spirit:version="icarus"/>`
90
91
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95
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97			`commoncommon`
98			`Verilog`
99
100
101			`fs-common`
102
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106
107			`sim:Simulation:`
108			`Verilog`
109
110
111			`fs-sim`
112
113
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116			`lint:Lint:`
117			`Verilog`
118
119
120			`fs-lint`
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141			`fs-common`
142
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148			`../verilog/tb.cpu0`
149			`verilogSource`
150			`fragment`
151
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167			`fs-sim`
168
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172			`../verilog/tb.ext`
173			`verilogSource`
174			`fragment`
175
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182	133	jt_eaton	`../verilog/common/top.tb.cpu0`
183	131	jt_eaton	`verilogSourcemodule`
184
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193			`fs-lint`
194
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196	133	jt_eaton	`../verilog/common/top.tb.cpu0`
197	131	jt_eaton	`verilogSourcemodule`
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