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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [xml/] [adv_dbg_if_jfifo_tb.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
adv_debug_sys
adv_dbg_if
jfifo_tb
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      adv_dbg_if_jfifo_tb
    
  

 
 
 

 
 
 
 
 
 


    JTAG_MODEL_DIVCNT     4'h4
    JTAG_MODEL_SIZE       4
    wb_addr_width       32
    wb_data_width       32

 
       
 
              
              Params
              
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="jfifo_dut.params"/>
             
              
 
 
              
              Bfm
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="bfm.design"/>
              
 
 
              
              Jfifo_Bfm
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="jfifo_bfm.design"/>
              
 
 
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 
 

 
 
 
 
 

 
 
 
 
   
      fs-common
 
 
 
      
        
        ../verilog/tb.jfifo
        verilogSource
        fragment
      
 
 
 
 
 
 
 
 
   
 
 
 
 
 
   
      fs-sim
 
 
      
        
        ../verilog/tb.ext
        verilogSource
        fragment
      
 
 
 
 
      
        
        ../verilog/common/adv_dbg_if_jfifo_tb
        verilogSourcemodule
      
 
 
 
 
   
 
 
   
      fs-lint
      
        
        ../verilog/common/adv_dbg_if_jfifo_tb
        verilogSourcemodule
      
 
 
   
 
 
 
 
 

 
 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [xml/] [adv_dbg_if_jfifo_tb.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`adv_debug_sys`
14			`adv_dbg_if`
15			`jfifo_tb`
16
17
18
19
20
21
22
23
24
25			`gen_verilog`
26			`104.0`
27			`none`
28			`common`
29			`./tools/verilog/gen_verilog`
30
31
32			`destination`
33	134	jt_eaton	`adv_dbg_if_jfifo_tb`
34	131	jt_eaton
35
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47
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49			`JTAG_MODEL_DIVCNT 4'h4`
50			`JTAG_MODEL_SIZE 4`
51			`wb_addr_width 32`
52			`wb_data_width 32`
53
54
55
56
57
58			`Params`
59
60
61			`spirit:library="adv_debug_sys"`
62			`spirit:name="adv_dbg_if"`
63			`spirit:version="jfifo_dut.params"/>`
64
65
66
67
68
69			`Bfm`
70
71			`spirit:library="adv_debug_sys"`
72			`spirit:name="adv_dbg_if"`
73			`spirit:version="bfm.design"/>`
74
75
76
77
78			`Jfifo_Bfm`
79
80			`spirit:library="adv_debug_sys"`
81			`spirit:name="adv_dbg_if"`
82			`spirit:version="jfifo_bfm.design"/>`
83
84
85
86
87
88
89			`icarus`
90
91
92			`spirit:library="Testbench"`
93			`spirit:name="toolflow"`
94			`spirit:version="icarus"/>`
95
96
97
98
99
100
101
102			`commoncommon`
103			`Verilog`
104
105
106			`fs-common`
107
108
109
110
111
112			`sim:Simulation:`
113			`Verilog`
114
115
116			`fs-sim`
117
118
119
120
121			`lint:Lint:`
122			`Verilog`
123
124
125			`fs-lint`
126
127
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134
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145
146			`fs-common`
147
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152			`../verilog/tb.jfifo`
153			`verilogSource`
154			`fragment`
155
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165
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170
171			`fs-sim`
172
173
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176			`../verilog/tb.ext`
177			`verilogSource`
178			`fragment`
179
180
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186	134	jt_eaton	`../verilog/common/adv_dbg_if_jfifo_tb`
187	131	jt_eaton	`verilogSourcemodule`
188
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195
196
197			`fs-lint`
198
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200	134	jt_eaton	`../verilog/common/adv_dbg_if_jfifo_tb`
201	131	jt_eaton	`verilogSourcemodule`
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