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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [xml/] [adv_dbg_if_jsp_tb.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
adv_debug_sys
adv_dbg_if
jsp_tb
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top.tb.jsp
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 

 
 
 
 
 
 


    JTAG_MODEL_DIVCNT     4'h4
    JTAG_MODEL_SIZE       4
    wb_addr_width       32
    wb_data_width       32

 
       
 
              
              Params
              
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="jsp_dut.params"/>
             
              
 
 
              
              Bfm
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="bfm.design"/>
              
 
 
              
              Jsp_Bfm
              
                                   spirit:library="adv_debug_sys"
                                   spirit:name="adv_dbg_if"
                                   spirit:version="jsp_bfm.design"/>
              
 
 
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 
 

 
 
 
 
 

 
 
 
 
   
      fs-common
 
 
 
 
 
      
        
        ../verilog/tb.jsp
        verilogSource
        fragment
      
 
 
 
 
 
 
 
 
   
 
 
 
 
 
   
      fs-sim
 
 
      
        
        ../verilog/tb.ext
        verilogSource
        fragment
      
 
 
 
 
      
        
        ../verilog/common/top.tb.jsp
        verilogSourcemodule
      
 
 
 
 
   
 
 
   
      fs-lint
      
        
        ../verilog/common/top.tb.jsp
        verilogSourcemodule
      
 
 
   
 
 
 
 
 

 
 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [adv_debug_sys/] [Hardware/] [adv_dbg_if/] [sim/] [testbenches/] [xml/] [adv_dbg_if_jsp_tb.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`opencores.org`
13			`adv_debug_sys`
14			`adv_dbg_if`
15			`jsp_tb`
16
17
18
19
20
21
22
23
24
25			`gen_verilog`
26			`104.0`
27			`none`
28			`common`
29			`./tools/verilog/gen_verilog`
30
31
32			`destination`
33	133	jt_eaton	`top.tb.jsp`
34	131	jt_eaton
35
36			`dest_dir`
37			`../verilog`
38
39
40			`top`
41
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55
56			`JTAG_MODEL_DIVCNT 4'h4`
57			`JTAG_MODEL_SIZE 4`
58			`wb_addr_width 32`
59			`wb_data_width 32`
60
61
62
63
64
65			`Params`
66
67
68			`spirit:library="adv_debug_sys"`
69			`spirit:name="adv_dbg_if"`
70			`spirit:version="jsp_dut.params"/>`
71
72
73
74
75
76			`Bfm`
77
78			`spirit:library="adv_debug_sys"`
79			`spirit:name="adv_dbg_if"`
80			`spirit:version="bfm.design"/>`
81
82
83
84
85			`Jsp_Bfm`
86
87			`spirit:library="adv_debug_sys"`
88			`spirit:name="adv_dbg_if"`
89			`spirit:version="jsp_bfm.design"/>`
90
91
92
93
94
95
96			`icarus`
97
98
99			`spirit:library="Testbench"`
100			`spirit:name="toolflow"`
101			`spirit:version="icarus"/>`
102
103
104
105
106
107
108
109			`commoncommon`
110			`Verilog`
111
112
113			`fs-common`
114
115
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117
118
119			`sim:Simulation:`
120			`Verilog`
121
122
123			`fs-sim`
124
125
126
127
128			`lint:Lint:`
129			`Verilog`
130
131
132			`fs-lint`
133
134
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153			`fs-common`
154
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161			`../verilog/tb.jsp`
162			`verilogSource`
163			`fragment`
164
165
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179
180			`fs-sim`
181
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185			`../verilog/tb.ext`
186			`verilogSource`
187			`fragment`
188
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195	133	jt_eaton	`../verilog/common/top.tb.jsp`
196	131	jt_eaton	`verilogSourcemodule`
197
198
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201
202
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204
205
206			`fs-lint`
207
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209	133	jt_eaton	`../verilog/common/top.tb.jsp`
210	131	jt_eaton	`verilogSourcemodule`
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