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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [rtl/] [verilog/] [top.jabc] - Blame information for rev 135

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Line No. Rev Author Line
1 131 jt_eaton 
assign   PosL = PosS;
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assign   ja_1_pad_out  = clk;
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assign   ja_2_pad_out  = reset;
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assign   ja_3_pad_out  = one_usec;
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assign   ja_4_pad_out  = 1'b0;
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assign   ja_7_pad_out  = 1'b0;
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assign   ja_8_pad_out  = 1'b0;
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assign   ja_9_pad_out  = 1'b0;
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assign   ja_10_pad_out = 1'b0;
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assign   jb_1_pad_out  = 1'b0;
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assign   jb_2_pad_out  = 1'b0;
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assign   jb_3_pad_out  = 1'b0;
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assign   jb_4_pad_out  = 1'b0;
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assign   jb_7_pad_out  = 1'b0;
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assign   jb_8_pad_out  = 1'b0;
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assign   jb_9_pad_out  = 1'b0;
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assign   jb_10_pad_out = 1'b0;
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assign   jc_1_pad_out  = 1'b1;
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assign   jc_2_pad_out  = 1'b0;
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assign   jc_3_pad_out  = 1'b1;
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assign   jc_4_pad_out  = 1'b0;
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assign   jc_7_pad_out  = 1'b0;
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assign   jc_8_pad_out  = 1'b0;
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assign   jc_9_pad_out  = 1'b0;
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assign   jc_10_pad_out = 1'b0;
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assign         pio_out       =  40'h0000000000;
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assign         pio_oe        =  40'h0000000000;
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