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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [rtl/] [xml/] [Nexys2_T6502_core.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
fpgas
Nexys2_T6502
core  default
 
 
 
 
 

 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      configuration
      core
    
    
      dest_dir
      io_ports
    
  

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top.T6502
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 
 
 
 
 
 
 

 
 
 

 
   
      fs-common
 
 
      
        
        ../verilog/top.jabc
        verilogSourcefragment
      
 
 
      
        
        ../verilog/top.gpio
        verilogSourcefragment
      
 
 
 
      
        
        ../verilog/top.rs_uart
        verilogSourcefragment
      
 
      
        ../verilog
        verilogSourcelibraryDir
      
 
 
 
   
 
 
   
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.T6502
        verilogSourcemodule
      
 
 
 
 
   
 
 
 
 
 

 
 
 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="fpgas"
                                   spirit:name="Nexys2_T6502"
                                   spirit:version="core.design"/>
              
 
 
              
              Core
 
              
              
                                   spirit:library="Nexys2"
                                   spirit:name="fpga"
                                   spirit:version="core"/>
              
 
 
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-sim
                     
              
 
      
 

 

 
 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [rtl/] [xml/] [Nexys2_T6502_core.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`fpgas`
39			`Nexys2_T6502`
40			`core default`
41
42
43
44
45
46
47
48	133	jt_eaton
49	131	jt_eaton
50	133	jt_eaton	`elab_verilog`
51			`102.1`
52			`none`
53			`:Simulation:`
54			`./tools/verilog/elab_verilog`
55
56
57			`configuration`
58			`core`
59
60
61			`dest_dir`
62			`io_ports`
63
64
65
66
67
68
69
70	131	jt_eaton	`gen_verilog`
71			`104.0`
72			`none`
73			`common`
74			`./tools/verilog/gen_verilog`
75
76
77			`destination`
78			`top.T6502`
79
80
81			`dest_dir`
82			`../verilog`
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103			`fs-common`
104
105
106
107
108			`../verilog/top.jabc`
109			`verilogSourcefragment`
110
111
112
113
114
115			`../verilog/top.gpio`
116			`verilogSourcefragment`
117
118
119
120
121
122
123			`../verilog/top.rs_uart`
124			`verilogSourcefragment`
125
126
127
128			`../verilog`
129			`verilogSourcelibraryDir`
130
131
132
133
134
135
136
137
138			`fs-sim`
139
140
141
142			`../verilog/copyright.v`
143			`verilogSourceinclude`
144
145
146
147
148			`../verilog/common/top.T6502`
149			`verilogSourcemodule`
150
151
152
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155
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162
163
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172
173			`Hierarchical`
174
175
176			`spirit:library="fpgas"`
177			`spirit:name="Nexys2_T6502"`
178			`spirit:version="core.design"/>`
179
180
181
182
183			`Core`
184
185
186
187			`spirit:library="Nexys2"`
188			`spirit:name="fpga"`
189			`spirit:version="core"/>`
190
191
192
193
194
195
196
197			`verilog`
198
199
200			`spirit:library="Testbench"`
201			`spirit:name="toolflow"`
202			`spirit:version="verilog"/>`
203
204
205
206
207
208
209
210
211			`commoncommon`
212			`Verilog`
213
214
215			`fs-common`
216
217
218
219
220			`sim:Simulation:`
221			`Verilog`
222
223
224			`fs-sim`
225
226
227
228
229
230			`syn:Synthesis:`
231			`Verilog`
232
233
234			`fs-sim`
235
236
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