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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [rtl/] [xml/] [Nexys2_T6502_core.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
fpgas
Nexys2_T6502
core  default
 
 
 
 
 

 
 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      Nexys2_T6502_core
    
  

 
 
 
 
 
 
 
 
 
 

 
 
 
 
 
 
 

       
 
              
              Hierarchical:*Simulation:*
              
                                   spirit:library="fpgas"
                                   spirit:name="Nexys2_T6502"
                                   spirit:version="core.design"/>
              
 
 
              
              Core:*Simulation:*
              
              
                                   spirit:library="Nexys2"
                                   spirit:name="fpga"
                                   spirit:version="core"/>
              
 
 
              
 
 
              
              verilog:*Simulation:*
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-sim
                     
              
 
      
 

 
 
 
 

 
   
      fs-common
 
 
      
        
        ../verilog/top.jabc
        verilogSourcefragment
      
 
 
      
        
        ../verilog/top.gpio
        verilogSourcefragment
      
 
 
 
      
        
        ../verilog/top.rs_uart
        verilogSourcefragment
      
 
      
        ../verilog
        verilogSourcelibraryDir
      
 
 
 
   
 
 
   
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/Nexys2_T6502_core
        verilogSourcemodule
      
 
 
 
 
   
 
 
 
 
 

 
 
 
 
 

 
 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [rtl/] [xml/] [Nexys2_T6502_core.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
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31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`fpgas`
39			`Nexys2_T6502`
40			`core default`
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48	133	jt_eaton
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53	131	jt_eaton	`gen_verilog`
54			`104.0`
55			`none`
56			`common`
57			`./tools/verilog/gen_verilog`
58
59
60			`destination`
61	134	jt_eaton	`Nexys2_T6502_core`
62	131	jt_eaton
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87	134	jt_eaton	`Hierarchical:Simulation:`
88	131	jt_eaton
89			`spirit:library="fpgas"`
90			`spirit:name="Nexys2_T6502"`
91			`spirit:version="core.design"/>`
92
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96	134	jt_eaton	`Core:Simulation:`
97	131	jt_eaton
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99			`spirit:library="Nexys2"`
100			`spirit:name="fpga"`
101			`spirit:version="core"/>`
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109	134	jt_eaton	`verilog:Simulation:`
110	131	jt_eaton
111
112			`spirit:library="Testbench"`
113			`spirit:name="toolflow"`
114			`spirit:version="verilog"/>`
115
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123			`commoncommon`
124			`Verilog`
125
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127			`fs-common`
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132			`sim:Simulation:`
133			`Verilog`
134
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136			`fs-sim`
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142			`syn:Synthesis:`
143			`Verilog`
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146			`fs-sim`
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154	134	jt_eaton
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160			`fs-common`
161
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165			`../verilog/top.jabc`
166			`verilogSourcefragment`
167
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172			`../verilog/top.gpio`
173			`verilogSourcefragment`
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180			`../verilog/top.rs_uart`
181			`verilogSourcefragment`
182
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185			`../verilog`
186			`verilogSourcelibraryDir`
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195			`fs-sim`
196
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199			`../verilog/copyright`
200			`verilogSourceinclude`
201
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205			`../verilog/common/Nexys2_T6502_core`
206			`verilogSourcemodule`
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224	131	jt_eaton
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