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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [rtl/] [xml/] [Nexys2_T6502_default.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
opencores.org
fpgas
Nexys2_T6502
default  default
 
 
 
 
 
 
 
 
 

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      configuration
      default
    
    
      destination
      top.T6502_default
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 
 

 
 
 
 
  
 
 
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.T6502_default
        verilogSourcemodule
      
 
    
 
 
 
 
 
 
  
 
 
 
 

 
 
  
 
              
              Hierarchical
 
              
                                   spirit:library="fpgas"
                                   spirit:name="Nexys2_T6502"
                                   spirit:version="fpga.design"/>
              
 
    
     Pad_Ring
 
     
     
                          spirit:library="Nexys2"
                          spirit:name="fpga"
                          spirit:version="jtag_padring"/>
     
    
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
 
    
    commoncommon
    Verilog
    
    fs-common
    
 
 
 
    
    sim:*Simulation:*
    Verilog
    
    fs-sim
    
 
 
    
    syn:*Synthesis:*
    Verilog
    
    fs-sim
    
 
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
 
 
 
 
 

 
 
 
 
 
 
 
 
 
 
 

 
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36			`opencores.org`
37			`fpgas`
38			`Nexys2_T6502`
39			`default default`
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54			`gen_verilog`
55			`104.0`
56			`none`
57			`common`
58			`./tools/verilog/gen_verilog`
59
60
61			`configuration`
62			`default`
63
64
65			`destination`
66			`top.T6502_default`
67
68
69			`dest_dir`
70			`../verilog`
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
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88
89
90			`fs-sim`
91
92
93
94			`../verilog/copyright.v`
95			`verilogSourceinclude`
96
97
98
99
100			`../verilog/common/top.T6502_default`
101			`verilogSourcemodule`
102
103
104
105
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107
108
109
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111
112
113
114
115
116
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118
119
120
121
122			`Hierarchical`
123
124
125			`spirit:library="fpgas"`
126			`spirit:name="Nexys2_T6502"`
127			`spirit:version="fpga.design"/>`
128
129
130
131			`Pad_Ring`
132
133
134
135			`spirit:library="Nexys2"`
136			`spirit:name="fpga"`
137			`spirit:version="jtag_padring"/>`
138
139
140
141
142			`verilog`
143
144
145			`spirit:library="Testbench"`
146			`spirit:name="toolflow"`
147			`spirit:version="verilog"/>`
148
149
150
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154
155
156
157
158			`commoncommon`
159			`Verilog`
160
161			`fs-common`
162
163
164
165
166
167			`sim:Simulation:`
168			`Verilog`
169
170			`fs-sim`
171
172
173
174
175			`syn:Synthesis:`
176			`Verilog`
177
178			`fs-sim`
179
180
181
182
183
184
185			`doc`
186
187
188			`spirit:library="Testbench"`
189			`spirit:name="toolflow"`
190			`spirit:version="documentation"/>`
191
192			`:Documentation:`
193			`Verilog`
194
195
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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [rtl/] [xml/] [Nexys2_T6502_default.xml] - Blame information for rev 131