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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [rtl/] [xml/] [Nexys2_T6502_default.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
opencores.org
fpgas
Nexys2_T6502
default  default
 

 
 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      Nexys2_T6502_default
    
  

 

 
 
 

 
  
 
              
              Hierarchical:*Simulation:*
              
                                   spirit:library="fpgas"
                                   spirit:name="Nexys2_T6502"
                                   spirit:version="fpga.design"/>
              
 
    
     Pad_Ring:*Simulation:*
 
     
     
                          spirit:library="Nexys2"
                          spirit:name="fpga"
                          spirit:version="jtag_padring"/>
     
    
 
              
              verilog:*Simulation:*
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
    
    commoncommon
    Verilog
    
    fs-common
    
 
 
 
    
    sim:*Simulation:*
    Verilog
    
    fs-sim
    
 
 
    
    syn:*Synthesis:*
    Verilog
    
    fs-sim
    
 
 
 
 
              
              doc:*Simulation:*
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
 
 
 

 
 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/Nexys2_T6502_default
        verilogSourcemodule
      
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/Nexys2_T6502_default
        verilogSourcemodule
      
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 
    
      fs-lint
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 
 
 
 
 
  
 
 
 
 
 
 

 
 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [rtl/] [xml/] [Nexys2_T6502_default.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36			`opencores.org`
37			`fpgas`
38			`Nexys2_T6502`
39			`default default`
40
41	133	jt_eaton
42	131	jt_eaton
43
44
45
46	134	jt_eaton
47	131	jt_eaton
48			`gen_verilog`
49			`104.0`
50			`none`
51			`common`
52			`./tools/verilog/gen_verilog`
53
54
55			`destination`
56	134	jt_eaton	`Nexys2_T6502_default`
57	131	jt_eaton
58
59
60
61
62
63
64
65
66
67
68
69
70	134	jt_eaton	`Hierarchical:Simulation:`
71	131	jt_eaton
72			`spirit:library="fpgas"`
73			`spirit:name="Nexys2_T6502"`
74			`spirit:version="fpga.design"/>`
75
76
77
78	134	jt_eaton	`Pad_Ring:Simulation:`
79	131	jt_eaton
80
81
82			`spirit:library="Nexys2"`
83			`spirit:name="fpga"`
84			`spirit:version="jtag_padring"/>`
85
86
87
88
89	134	jt_eaton	`verilog:Simulation:`
90	131	jt_eaton
91
92			`spirit:library="Testbench"`
93			`spirit:name="toolflow"`
94			`spirit:version="verilog"/>`
95
96
97
98
99
100
101			`commoncommon`
102			`Verilog`
103
104			`fs-common`
105
106
107
108
109
110			`sim:Simulation:`
111			`Verilog`
112
113			`fs-sim`
114
115
116
117
118			`syn:Synthesis:`
119			`Verilog`
120
121			`fs-sim`
122
123
124
125
126
127
128	134	jt_eaton	`doc:Simulation:`
129	131	jt_eaton
130
131			`spirit:library="Testbench"`
132			`spirit:name="toolflow"`
133			`spirit:version="documentation"/>`
134
135			`:Documentation:`
136			`Verilog`
137
138
139
140
141
142
143
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145
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147
148
149
150
151	134	jt_eaton
152	131	jt_eaton
153	134	jt_eaton
154			`fs-sim`
155	131	jt_eaton
156	134	jt_eaton
157
158			`../verilog/copyright`
159			`verilogSourceinclude`
160
161	131	jt_eaton
162	134	jt_eaton
163
164			`../verilog/common/Nexys2_T6502_default`
165			`verilogSourcemodule`
166
167	131	jt_eaton
168	134	jt_eaton
169			`dest_dir`
170			`../views/sim/`
171			`verilogSourcelibraryDir`
172
173	131	jt_eaton
174	134	jt_eaton
175	131	jt_eaton
176
177	134	jt_eaton
178
179
180			`fs-syn`
181
182
183
184			`../verilog/copyright`
185			`verilogSourceinclude`
186
187
188
189
190			`../verilog/common/Nexys2_T6502_default`
191			`verilogSourcemodule`
192
193
194
195			`dest_dir`
196			`../views/syn/`
197			`verilogSourcelibraryDir`
198
199
200
201
202
203
204
205
206
207			`fs-lint`
208
209
210			`dest_dir`
211			`../views/syn/`
212			`verilogSourcelibraryDir`
213
214
215
216
217
218
219
220
221
222
223
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232	131	jt_eaton
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