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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [rtl/] [xml/] [Nexys2_T6502_default.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
opencores.org
fpgas
Nexys2_T6502
default
 

 
 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      Nexys2_T6502_default
    
  

 

 
 
 

 
 
 
                
                        
                                Hierarchical
                                
                        
                
 
 
 
  
 
              
              Hierarchical:*Simulation:*
 
     Hierarchical
 
              
 
    
     Pad_Ring:*Simulation:*
 
     
     
                          ipxact:library="Nexys2"
                          ipxact:name="fpga"
                          ipxact:version="jtag_padring"/>
     
    
 
              
              verilog:*Simulation:*
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
    
    common:*common:*
    Verilog
    
    fs-common
    
 
 
 
    
    sim:*Simulation:*
    Verilog
    
    fs-sim
    
 
 
    
    syn:*Synthesis:*
    Verilog
    
    fs-sim
    
 
 
 
 
              
              doc:*Simulation:*
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
 
 
 

 
 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/Nexys2_T6502_default
        verilogSourcemodule
      
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/Nexys2_T6502_default
        verilogSourcemodule
      
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 
    
      fs-lint
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 
 
 
 
 
  
 
 
 
 
 
 

 
 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [rtl/] [xml/] [Nexys2_T6502_default.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36			`opencores.org`
37			`fpgas`
38			`Nexys2_T6502`
39			`default`
40	131	jt_eaton
41	135	jt_eaton
42	131	jt_eaton
43
44
45
46	134	jt_eaton
47	135	jt_eaton
48			`gen_verilog`
49			`104.0`
50			`none`
51			`:common:`
52			`tools/verilog/gen_verilog`
53
54
55			`destination`
56			`Nexys2_T6502_default`
57
58
59
60	131	jt_eaton
61	135	jt_eaton
62	131	jt_eaton
63
64
65	135	jt_eaton
66	131	jt_eaton
67
68
69	135	jt_eaton
70
71			`Hierarchical`
72
73
74
75
76
77
78
79
80
81			`Hierarchical:Simulation:`
82
83			`Hierarchical`
84
85
86
87
88			`Pad_Ring:Simulation:`
89	131	jt_eaton
90	135	jt_eaton
91
92			`ipxact:library="Nexys2"`
93			`ipxact:name="fpga"`
94			`ipxact:version="jtag_padring"/>`
95
96
97	131	jt_eaton
98	135	jt_eaton
99			`verilog:Simulation:`
100
101
102			`ipxact:library="Testbench"`
103			`ipxact:name="toolflow"`
104			`ipxact:version="verilog"/>`
105
106
107	131	jt_eaton
108
109
110	135	jt_eaton
111			`common:common:`
112			`Verilog`
113
114			`fs-common`
115
116	131	jt_eaton
117
118
119	135	jt_eaton
120			`sim:Simulation:`
121			`Verilog`
122
123			`fs-sim`
124
125	131	jt_eaton
126
127	135	jt_eaton
128			`syn:Synthesis:`
129			`Verilog`
130
131			`fs-sim`
132
133	131	jt_eaton
134
135
136
137	135	jt_eaton
138			`doc:Simulation:`
139
140
141			`ipxact:library="Testbench"`
142			`ipxact:name="toolflow"`
143			`ipxact:version="documentation"/>`
144
145			`:Documentation:`
146			`Verilog`
147
148	131	jt_eaton
149
150	135	jt_eaton
151	131	jt_eaton
152
153
154
155
156	135	jt_eaton
157	131	jt_eaton
158
159
160
161	135	jt_eaton
162	131	jt_eaton
163	135	jt_eaton
164			`fs-sim`
165	131	jt_eaton
166	135	jt_eaton
167
168			`../verilog/copyright`
169			`verilogSourceinclude`
170
171	131	jt_eaton
172	135	jt_eaton
173
174			`../verilog/common/Nexys2_T6502_default`
175			`verilogSourcemodule`
176
177	131	jt_eaton
178	135	jt_eaton
179			`dest_dir`
180			`../views/sim/`
181			`verilogSourcelibraryDir`
182
183	131	jt_eaton
184	135	jt_eaton
185	131	jt_eaton
186
187	134	jt_eaton
188
189	135	jt_eaton
190			`fs-syn`
191	134	jt_eaton
192	135	jt_eaton
193
194			`../verilog/copyright`
195			`verilogSourceinclude`
196
197	134	jt_eaton
198	135	jt_eaton
199
200			`../verilog/common/Nexys2_T6502_default`
201			`verilogSourcemodule`
202
203	134	jt_eaton
204	135	jt_eaton
205			`dest_dir`
206			`../views/syn/`
207			`verilogSourcelibraryDir`
208
209	134	jt_eaton
210	135	jt_eaton
211	134	jt_eaton
212
213
214
215
216	135	jt_eaton
217			`fs-lint`
218	134	jt_eaton
219	135	jt_eaton
220			`dest_dir`
221			`../views/syn/`
222			`verilogSourcelibraryDir`
223
224	134	jt_eaton
225	135	jt_eaton
226	134	jt_eaton
227
228
229
230
231
232
233
234
235	135	jt_eaton
236	134	jt_eaton
237
238
239
240
241
242	135	jt_eaton
243	131	jt_eaton
244
245
246
247
248