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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [sim/] [icarus/] [jtag/] [test_define] - Blame information for rev 133

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Line No. Rev Author Line
1 133 jt_eaton 
 
2 
reg actual;
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parameter   EXTEST          =   4'b0000;
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parameter   SAMPLE          =   4'b0001;
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parameter   HIGHZ_MODE      =   4'b0010;
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parameter   CHIP_ID_ACCESS  =   4'b0011;
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parameter   CLAMP           =   4'b1000;
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parameter   RPC_DATA        =   4'b1010;
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parameter   RPC_ADD         =   4'b1001;
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parameter   BYPASS          =   4'b1111;
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parameter   INST_RETURN     =   4'b1101;
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initial
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begin
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$display("              ");
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$display("              ===================================================");
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$display("              Test Start");
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$display("              ===================================================");
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$display("              ");
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test.cg.next(20);
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fork
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begin
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test.uart_model.rcv_byte(8'h0d);
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test.uart_model.rcv_byte(8'h0a);
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test.uart_model.rcv_byte(8'h4b);
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test.uart_model.rcv_byte(8'h49);
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test.uart_model.rcv_byte(8'h4d);
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test.uart_model.rcv_byte(8'h0d);
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test.uart_model.rcv_byte(8'h0a);
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test.cg.next(4000);
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end
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begin
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$display("              ");
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$display("              ===================================================");
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$display("              JTAG Test Start");
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$display("              ===================================================");
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$display("              ");
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test.cg.next(2);
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test.jtag_model.enable_tclk;
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test.cg.next(20);
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test.jtag_model.enable_trst_n;
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test.jtag_model.enable_reset;
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test.jtag_model.init;
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test.cg.next(10);
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test.jtag_model.LoadTapInst(EXTEST,INST_RETURN);
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test.cg.next(100);
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test.jtag_model.LoadTapInst(CLAMP,INST_RETURN);
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test.cg.next(100);
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test.jtag_model.LoadTapInst(CHIP_ID_ACCESS,INST_RETURN);
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test.jtag_model.Shift_Cmp_32(32'ha5a5a5a5,32'hf1c2e093);
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test.SW_reg   = 8'h00;
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test.cg.next(100);
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test.jtag_model.LoadTapInst(RPC_DATA,INST_RETURN);
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test.cg.next(1000);
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Shift_Cmp_8(8'ha5,8'h00);
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test.SW_reg   = 8'h00;
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test.cg.next(1000);
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Shift_Cmp_8(8'hf0,8'h00);
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test.cg.next(100);
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test.jtag_model.LoadTapInst(RPC_ADD,INST_RETURN);
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test.cg.next(100);
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Shift_Cmp_18(18'h38000,18'h00004);
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test.cg.next(500);
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Shift_Cmp_18(18'h1fc21,18'h00004);
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test.cg.next(500);
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Shift_Cmp_18(18'h1f821,18'h0fe14);
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test.cg.next(500);
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Shift_Cmp_18(18'h1f021,18'h0fc14);
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test.cg.next(500);
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Shift_Cmp_18(18'h1c021,18'h0f814);
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test.cg.next(500);
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Shift_Cmp_18(18'h18021,18'h0e014);
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test.cg.next(500);
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Shift_Cmp_18(18'h10021,18'h0c014);
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test.cg.next(500);
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Shift_Cmp_18(18'h00021,18'h08014);
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test.cg.next(500);
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Shift_Cmp_18(18'h1fe21,18'h00014);
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test.cg.next(500);
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test.jtag_model.LoadTapInst(BYPASS,INST_RETURN);
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test.cg.next(100);
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end
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join
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test.cg.exit;
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end
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task automatic  Shift_Cmp_8;    // Initialize boundary register with outputs disabled
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                         // This tasks starts at RT_IDLE and ends at SHIFT_DR
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  parameter [15:0] LENGTH =  8;
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  input [LENGTH:1]  Dataout;
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  input [LENGTH:1]  DataExp;
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  integer i;
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  reg [LENGTH:1]  DataBack;
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  begin
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    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
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    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
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    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR
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    for (i = 1; i <= LENGTH; i = i+1)
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       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
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    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );
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   if (DataBack  !== DataExp )
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   begin
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   test.cg.fail  (" Shift_cmp  receive error  ");
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   end
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    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR
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    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
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  end
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endtask // ShiftRegister
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task automatic  Shift_Cmp_18;    // Initialize boundary register with outputs disabled
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                         // This tasks starts at RT_IDLE and ends at SHIFT_DR
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  parameter [15:0] LENGTH =  18;
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  input [LENGTH:1]  Dataout;
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  input [LENGTH:1]  DataExp;
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  integer i;
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  reg [LENGTH:1]  DataBack;
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  begin
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    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
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    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
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    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR
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    for (i = 1; i <= LENGTH; i = i+1)
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       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
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    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );
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   if (DataBack  !== DataExp )
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   begin
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   test.cg.fail  (" Shift_cmp  receive error  ");
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   end
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    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR
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    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
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  end
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endtask // ShiftRegister
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