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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [sim/] [testbenches/] [verilog/] [tb.ext] - Blame information for rev 133

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Line No. Rev Author Line
1 131 jt_eaton
assign A_CLK   = clk;
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assign CTS     = reset;
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pullup pu_ramwait  ( RAMWAIT   );
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pullup pu_memdb_0  ( MEMDB[0]  );
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pullup pu_memdb_1  ( MEMDB[1]  );
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pullup pu_memdb_2  ( MEMDB[2]  );
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pullup pu_memdb_3  ( MEMDB[3]  );
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pullup pu_memdb_4  ( MEMDB[4]  );
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pullup pu_memdb_5  ( MEMDB[5]  );
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pullup pu_memdb_6  ( MEMDB[6]  );
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pullup pu_memdb_7  ( MEMDB[7]  );
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pullup pu_memdb_8  ( MEMDB[8]  );
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pullup pu_memdb_9  ( MEMDB[9]  );
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pullup pu_memdb_10 ( MEMDB[10] );
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pullup pu_memdb_11 ( MEMDB[11] );
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pullup pu_memdb_12 ( MEMDB[12] );
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pullup pu_memdb_13 ( MEMDB[13] );
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pullup pu_memdb_14 ( MEMDB[14] );
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pullup pu_memdb_15 ( MEMDB[15] );
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pullup pu_flashststs ( FLASHSTSTS );
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pullup pu_jtag ( JTAG_TDO );
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pullup pu_jtag ( PS2C );
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pullup pu_jtag ( PS2D );
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reg [7:0] SW_reg;
31 133 jt_eaton
reg [3:0] BTN_reg;
32 131 jt_eaton
 
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initial
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begin
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SW_reg  = 8'h00;
36 133 jt_eaton
BTN_reg = 4'h0;
37 131 jt_eaton
end
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assign SW = SW_reg;
40 133 jt_eaton
assign BTN = BTN_reg;
41 131 jt_eaton
 
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assign STOP = 1'b0;
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assign BAD = 1'b0;
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