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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [sim/] [testbenches/] [xml/] [Nexys2_T6502_default_tb.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
opencores.org
fpgas
Nexys2_T6502
default_tb
 
 
 
 
 

 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      configuration
      default
    
    
      destination
      top.T6502_tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 

 
 
 
 
 


    JTAG_MODEL_DIVCNT 4'h4     
    JTAG_MODEL_SIZE   4        
    UART_MODEL_CLKCNT 5'b11001 
    UART_MODEL_SIZE   5        
    PS2_MODEL_CLKCNT  10'h177  
    PS2_MODEL_SIZE    10       
 

       
 
 
 
              
              Params
              
              
                                   spirit:library="fpgas"
                                   spirit:name="Nexys2_T6502"
                                   spirit:version="default_dut.params"/>
              
              
 
 
 
              
              Bfm
              
                                   spirit:library="fpgas"
                                   spirit:name="Nexys2_T6502"
                                   spirit:version="bfm.design"/>
              
 
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 

 
 
 
  
 
 
 
    
      fs-common
 
      
        
        ../verilog/sram.load
        verilogSourcefragment
      
 
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
 
 
    
 
 
 
 
    
      fs-sim
 
      
        
        ../verilog/common/top.T6502_tb
        verilogSourcemodule
      
 
    
 
 
    
      fs-lint
 
      
        
        ../verilog/common/top.T6502_tb
        verilogSourcemodule
      
 
 
    
 
 
 
 
 
 
  
 
 
 

 
 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [sim/] [testbenches/] [xml/] [Nexys2_T6502_default_tb.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36			`opencores.org`
37			`fpgas`
38			`Nexys2_T6502`
39			`default_tb`
40
41
42
43
44
45
46
47
48			`gen_verilog`
49			`104.0`
50			`none`
51			`common`
52			`./tools/verilog/gen_verilog`
53
54
55	133	jt_eaton	`configuration`
56			`default`
57
58
59	131	jt_eaton	`destination`
60			`top.T6502_tb`
61
62
63			`dest_dir`
64			`../verilog`
65
66
67			`top`
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82			`JTAG_MODEL_DIVCNT 4'h4`
83			`JTAG_MODEL_SIZE 4`
84			`UART_MODEL_CLKCNT 5'b11001`
85			`UART_MODEL_SIZE 5`
86			`PS2_MODEL_CLKCNT 10'h177`
87			`PS2_MODEL_SIZE 10`
88
89
90
91
92
93
94
95			`Params`
96
97
98			`spirit:library="fpgas"`
99			`spirit:name="Nexys2_T6502"`
100			`spirit:version="default_dut.params"/>`
101
102
103
104
105
106
107			`Bfm`
108
109			`spirit:library="fpgas"`
110			`spirit:name="Nexys2_T6502"`
111			`spirit:version="bfm.design"/>`
112
113
114
115
116
117			`icarus`
118
119
120			`spirit:library="Testbench"`
121			`spirit:name="toolflow"`
122			`spirit:version="icarus"/>`
123
124
125
126
127
128
129
130			`commoncommon`
131			`Verilog`
132
133
134			`fs-common`
135
136
137
138
139
140			`sim:Simulation:`
141			`Verilog`
142
143
144			`fs-sim`
145
146
147
148
149			`lint:Lint:`
150			`Verilog`
151
152
153			`fs-lint`
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170			`fs-common`
171
172
173
174			`../verilog/sram.load`
175			`verilogSourcefragment`
176
177
178
179
180
181			`../verilog/tb.ext`
182			`verilogSourcefragment`
183
184
185
186
187
188
189
190
191
192
193			`fs-sim`
194
195
196
197			`../verilog/common/top.T6502_tb`
198			`verilogSourcemodule`
199
200
201
202
203
204
205			`fs-lint`
206
207
208
209			`../verilog/common/top.T6502_tb`
210			`verilogSourcemodule`
211
212
213
214
215
216
217
218
219
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