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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [sim/] [testbenches/] [xml/] [Nexys2_T6502_default_tb.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
opencores.org
fpgas
Nexys2_T6502
default_tb
 
 
 
 
 

 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      Nexys2_T6502_default_tb
    
  

 
 
 

 
 
 
 
 


    JTAG_MODEL_DIVCNT 4'h4     
    JTAG_MODEL_SIZE   4        
    UART_MODEL_CLKCNT 5'b11001 
    UART_MODEL_SIZE   5        
    PS2_MODEL_CLKCNT  10'h177  
    PS2_MODEL_SIZE    10       
 

       
 
 
 
              
              Params
              
              
                                   spirit:library="fpgas"
                                   spirit:name="Nexys2_T6502"
                                   spirit:version="default_dut.params"/>
              
              
 
 
 
              
              Bfm
              
                                   spirit:library="fpgas"
                                   spirit:name="Nexys2_T6502"
                                   spirit:version="bfm.design"/>
              
 
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 

 
 
 
  
 
 
 
    
      fs-common
 
      
        
        ../verilog/sram.load
        verilogSourcefragment
      
 
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
 
 
    
 
 
 
 
    
      fs-sim
 
      
        
        ../verilog/common/Nexys2_T6502_default_tb
        verilogSourcemodule
      
 
    
 
 
 
 
 
 
 
  
 
 
 

 
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36			`opencores.org`
37			`fpgas`
38			`Nexys2_T6502`
39			`default_tb`
40
41
42
43
44
45
46
47
48			`gen_verilog`
49			`104.0`
50			`none`
51			`common`
52			`./tools/verilog/gen_verilog`
53
54
55			`destination`
56	134	jt_eaton	`Nexys2_T6502_default_tb`
57	131	jt_eaton
58
59
60
61
62
63
64
65
66
67
68
69
70
71			`JTAG_MODEL_DIVCNT 4'h4`
72			`JTAG_MODEL_SIZE 4`
73			`UART_MODEL_CLKCNT 5'b11001`
74			`UART_MODEL_SIZE 5`
75			`PS2_MODEL_CLKCNT 10'h177`
76			`PS2_MODEL_SIZE 10`
77
78
79
80
81
82
83
84			`Params`
85
86
87			`spirit:library="fpgas"`
88			`spirit:name="Nexys2_T6502"`
89			`spirit:version="default_dut.params"/>`
90
91
92
93
94
95
96			`Bfm`
97
98			`spirit:library="fpgas"`
99			`spirit:name="Nexys2_T6502"`
100			`spirit:version="bfm.design"/>`
101
102
103
104
105
106			`icarus`
107
108
109			`spirit:library="Testbench"`
110			`spirit:name="toolflow"`
111			`spirit:version="icarus"/>`
112
113
114
115
116
117
118
119			`commoncommon`
120			`Verilog`
121
122
123			`fs-common`
124
125
126
127
128
129			`sim:Simulation:`
130			`Verilog`
131
132
133			`fs-sim`
134
135
136
137
138			`lint:Lint:`
139			`Verilog`
140
141
142			`fs-lint`
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159			`fs-common`
160
161
162
163			`../verilog/sram.load`
164			`verilogSourcefragment`
165
166
167
168
169
170			`../verilog/tb.ext`
171			`verilogSourcefragment`
172
173
174
175
176
177
178
179
180
181
182			`fs-sim`
183
184
185
186	134	jt_eaton	`../verilog/common/Nexys2_T6502_default_tb`
187	131	jt_eaton	`verilogSourcemodule`
188
189
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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [sim/] [testbenches/] [xml/] [Nexys2_T6502_default_tb.xml] - Blame information for rev 134