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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [syn/] [chips/] [xml/] [Nexys2_T6502_chip.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
opencores.org
fpgas
Nexys2_T6502
chip
 
 
 
 
 
 
 
 
 

 

  elab_verilog_syn
  103.0
  none
  :*Synthesis:*
  ./tools/verilog/elab_verilog
 
   
   
      env
      syn
    
    
      tool
      ise
    
    
      unit
      chip
    
  
 
 
 

 

 
 
 
 
 

 
 
  
 
 
 
 
    
    syn:*Synthesis:*
    Verilog
    
    
 
 
 
 
 
 
 

 
 
 

 
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36			`opencores.org`
37			`fpgas`
38			`Nexys2_T6502`
39			`chip`
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52			`elab_verilog_syn`
53			`103.0`
54			`none`
55			`:Synthesis:`
56			`./tools/verilog/elab_verilog`
57
58
59
60			`env`
61			`syn`
62
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64			`tool`
65			`ise`
66
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68			`unit`
69			`chip`
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92			`syn:Synthesis:`
93			`Verilog`
94
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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [syn/] [chips/] [xml/] [Nexys2_T6502_chip.xml] - Blame information for rev 131